公开(公告)号：US11431646B2

公开(公告)日：2022-08-30

申请号：US17093200

申请日：2020-11-09

申请人： Intel Corporation

发明人： Kulwinder Singh Dhanoa

IPC分类号： H04L47/50 ,  H04L47/52 ,  H04L47/628 ,  H04L47/62 ,  H04L47/80 ,  H04L47/36 ,  H04L67/61 ,  H04L47/10

摘要： Systems and methods are disclosed for enhancing network performance by using modified traffic control (e.g., rate limiting and/or scheduling) techniques to control a rate of packet (e.g., data packet) traffic to a queue scheduled by a Quality of Service (QoS) engine for reading and transmission. In particular, the QoS engine schedules packets using estimated packet sizes before an actual packet size is known by a direct memory access (DMA) engine coupled to the QoS engine. The QoS engine subsequently compensates for discrepancies between the estimated packet sizes and actual packet sizes (e.g., when the DMA engine has received an actual packet size of the scheduled packet). Using these modified traffic control techniques that leverage estimating packet sizes may reduce and/or eliminate latency introduced due to determining actual packet sizes.

公开(公告)号：US10834009B2

公开(公告)日：2020-11-10

申请号：US16357019

申请日：2019-03-18

申请人： Intel Corporation

发明人： Kulwinder Singh Dhanoa

IPC分类号： H04L12/869 ,  H04L12/873 ,  H04L12/863 ,  H04L12/927 ,  H04L12/805 ,  H04L29/08 ,  H04L12/801

摘要： Systems and methods are disclosed for enhancing network performance by using modified traffic control (e.g., rate limiting and/or scheduling) techniques to control a rate of packet (e.g., data packet) traffic to a queue scheduled by a Quality of Service (QoS) engine for reading and transmission. In particular, the QoS engine schedules packets using estimated packet sizes before an actual packet size is known by a direct memory access (DMA) engine coupled to the QoS engine. The QoS engine subsequently compensates for discrepancies between the estimated packet sizes and actual packet sizes (e.g., when the DMA engine has received an actual packet size of the scheduled packet). Using these modified traffic control techniques that leverage estimating packet sizes may reduce and/or eliminate latency introduced due to determining actual packet sizes.

公开(公告)号：US20230342418A1

公开(公告)日：2023-10-26

申请号：US18217011

申请日：2023-06-30

申请人： Intel Corporation

发明人： Tolga Ayhan ,  Mahshid Shahmohammadian ,  Kulwinder Singh Dhanoa ,  Nima Safari

IPC分类号： G06F17/16

CPC分类号： G06F17/16

摘要： Integrated circuit devices, methods, and circuitry for implementing and using a systolic array are provided. Such circuitry may include processing elements arranged in a triangular systolic array. The processing elements may receive an input matrix and perform Cholesky decomposition in a first stage, triangular matrix inversion in a second stage, and matrix multiplication in a third stage to produce an inverse of the input matrix as an output matrix.

公开(公告)号：US20210083986A1

公开(公告)日：2021-03-18

申请号：US17093200

申请日：2020-11-09

申请人： Intel Corporation

发明人： Kulwinder Singh Dhanoa

IPC分类号： H04L12/869 ,  H04L12/873 ,  H04L12/863 ,  H04L12/927

摘要： Systems and methods are disclosed for enhancing network performance by using modified traffic control (e.g., rate limiting and/or scheduling) techniques to control a rate of packet (e.g., data packet) traffic to a queue scheduled by a Quality of Service (QoS) engine for reading and transmission. In particular, the QoS engine schedules packets using estimated packet sizes before an actual packet size is known by a direct memory access (DMA) engine coupled to the QoS engine. The QoS engine subsequently compensates for discrepancies between the estimated packet sizes and actual packet sizes (e.g., when the DMA engine has received an actual packet size of the scheduled packet). Using these modified traffic control techniques that leverage estimating packet sizes may reduce and/or eliminate latency introduced due to determining actual packet sizes.

公开(公告)号：US20190215277A1

公开(公告)日：2019-07-11

申请号：US16357019

申请日：2019-03-18

申请人： Intel Corporation

发明人： Kulwinder Singh Dhanoa

IPC分类号： H04L12/869 ,  H04L12/873 ,  H04L12/863 ,  H04L12/927

摘要： Systems and methods are disclosed for enhancing network performance by using modified traffic control (e.g., rate limiting and/or scheduling) techniques to control a rate of packet (e.g., data packet) traffic to a queue scheduled by a Quality of Service (QoS) engine for reading and transmission. In particular, the QoS engine schedules packets using estimated packet sizes before an actual packet size is known by a direct memory access (DMA) engine coupled to the QoS engine. The QoS engine subsequently compensates for discrepancies between the estimated packet sizes and actual packet sizes (e.g., when the DMA engine has received an actual packet size of the scheduled packet). Using these modified traffic control techniques that leverage estimating packet sizes may reduce and/or eliminate latency introduced due to determining actual packet sizes.