公开(公告)号：US20180130902A1

公开(公告)日：2018-05-10

申请号：US15573110

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Xiaodong YANG ,  Jui-Yen LIN ,  Kinyip PHOA ,  Nidhi NIDHI ,  Yi Wei CHEN ,  Kun-Huan SHIH ,  Walid M. HAFEZ ,  Curtis TSAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/94 ,  H01L23/48

CPC classification number: H01L29/7813 ,  H01L23/481 ,  H01L29/0653 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/945

Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.