公开(公告)号：US20200251470A1

公开(公告)日：2020-08-06

申请号：US16846896

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Curtis TSAI ,  Chia-Hong JAN ,  Jeng-Ya David YEH ,  Joodong PARK ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/49 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

公开(公告)号：US20200273887A1

公开(公告)日：2020-08-27

申请号：US15931881

申请日：2020-05-14

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20240113128A1

公开(公告)日：2024-04-04

申请号：US18538795

申请日：2023-12-13

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20230299087A1

公开(公告)日：2023-09-21

申请号：US18140931

申请日：2023-04-28

Applicant: Intel Corporation

Inventor： Curtis TSAI ,  Chia-Hong JAN ,  Jeng-Ya David YEH ,  Joodong PARK ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/66484 ,  H01L29/408 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/40114 ,  H01L21/823456 ,  H01L27/0924 ,  H01L29/42364 ,  H01L29/7831 ,  H01L29/517

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

公开(公告)号：US20180130902A1

公开(公告)日：2018-05-10

申请号：US15573110

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Xiaodong YANG ,  Jui-Yen LIN ,  Kinyip PHOA ,  Nidhi NIDHI ,  Yi Wei CHEN ,  Kun-Huan SHIH ,  Walid M. HAFEZ ,  Curtis TSAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/94 ,  H01L23/48

CPC classification number: H01L29/7813 ,  H01L23/481 ,  H01L29/0653 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/945

Abstract: A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.

公开(公告)号：US20250031446A1

公开(公告)日：2025-01-23

申请号：US18903667

申请日：2024-10-01

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20220102385A1

公开(公告)日：2022-03-31

申请号：US17033418

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  Brian GREENE ,  Avyaya JAYANTHINARASIMHAM ,  Ayan KAR ,  Benjamin ORR ,  Chung-Hsun LIN ,  Curtis TSAI ,  Kalyan KOLLURU ,  Kevin FISCHER ,  Lin HU ,  Nathan JACK ,  Nicholas THOMSON ,  Rishabh MEHANDRU ,  Rui MA ,  Sabih OMAR

IPC: H01L27/12

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

公开(公告)号：US20180040637A1

公开(公告)日：2018-02-08

申请号：US15784318

申请日：2017-10-16

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20230207569A1

公开(公告)日：2023-06-29

申请号：US18111313

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/1211 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/66545 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L29/6681 ,  H01L29/51 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823437 ,  H01L29/513 ,  H01L29/42356 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/6656

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20230197779A1

公开(公告)日：2023-06-22

申请号：US17556602

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Marni NABORS ,  Mauro J. KOBRINSKY ,  Conor P. PULS ,  Kevin FISCHER ,  Curtis TSAI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L23/48

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L23/481

Abstract: Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.