公开(公告)号：US20180189587A1

公开(公告)日：2018-07-05

申请号：US15826524

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Dipan Kumar Mandal ,  Om J. Omer ,  Lance E. Hacking ,  James Radford ,  Sreenivas Subramoney ,  Eagle Jones ,  Gautham N. Chinya

IPC: G06K9/00 ,  G06K9/46 ,  G06K9/20 ,  G06K9/62

CPC classification number: G06K9/00973 ,  G06K9/00664 ,  G06K9/2054 ,  G06K9/46 ,  G06K9/6202 ,  G06K9/6267 ,  G06K2009/3291 ,  G06K2009/4666 ,  G06T7/246 ,  G06T7/579 ,  G06T2207/10016

Abstract: Aspects of the present disclosure relates to technologies (systems, devices, methods, etc.) for performing feature detection and/or feature tracking based on image data. In embodiments, the technologies include or leverage a SLAM hardware accelerator (SWA) that includes a feature detection component and optionally a feature tracking component. The feature detection component may be configured to perform feature detection on working data encompassed by a sliding window. The feature tracking component is configured to perform feature tracking operations to track one or more detected features, e.g., using normalized cross correlation (NCC) or another method.

公开(公告)号：US09189439B2

公开(公告)日：2015-11-17

申请号：US14141574

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Ramana Rachakonda ,  Lance E. Hacking ,  Mahesh K. Reddy ,  Lori R. Borger ,  Chee Hak Teh ,  Pawitter P. Bhatia ,  John P. Lee

IPC: G06F15/78 ,  G06F13/40 ,  G01R31/3185

CPC classification number: G06F13/40 ,  G01R31/318572 ,  G06F15/7807 ,  G06F15/7842 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有第一和第二核心的系统级芯片（SoC），耦合到核心的接口逻辑，耦合到接口逻辑的芯片组逻辑以及耦合在芯片组逻辑之间的虚拟防火墙逻辑 和第二核心。 接口逻辑可以包括防火墙逻辑，总线逻辑和测试逻辑，并且芯片组逻辑可以包括存储器控制器以提供与耦合到SoC的存储器的通信。 在一些系统实现中，无论是在测试操作还是功能操作期间，在正常操作期间可以禁用第二个内核以提供单个核心SoC，从而在许多不同实现中使SoC的灵活性更高。 描述和要求保护其他实施例。