公开(公告)号：US20250036591A1

公开(公告)日：2025-01-30

申请号：US18912321

申请日：2024-10-10

Applicant: Intel Corporation

Inventor： Ilya K. Ganusov ,  Ashish Gupta ,  Chee Hak Teh ,  Sean R. Atsatt ,  Scott Jeremy Weber ,  Parivallal Kannan ,  Aman Gupta ,  Gary Brian Wallichs

IPC: G06F15/78 ,  H04L45/60 ,  H04L49/109

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

公开(公告)号：US12164462B2

公开(公告)日：2024-12-10

申请号：US17132663

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ilya K. Ganusov ,  Ashish Gupta ,  Chee Hak Teh ,  Sean R. Atsatt ,  Scott Jeremy Weber ,  Parivallal Kannan ,  Aman Gupta ,  Gary Brian Wallichs

IPC: G06F15/78 ,  H04L45/60 ,  H04L49/109

Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.

公开(公告)号：US20220198115A1

公开(公告)日：2022-06-23

申请号：US17392218

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Ankireddy Nalamalpu ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Sean R. Atsatt ,  Lai Guan Tang

IPC: G06F30/34 ,  H03K19/17736 ,  H04L12/43 ,  G06F15/78 ,  H03K19/17796

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

公开(公告)号：US11188255B2

公开(公告)日：2021-11-30

申请号：US15938740

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  Kevin Chao Ing Teoh

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/00 ,  G06F13/28

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.

公开(公告)号：US20190303039A1

公开(公告)日：2019-10-03

申请号：US15938740

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  Kevin Chao Ing Teoh

IPC: G06F3/06 ,  G06F13/16

Abstract: An integrated circuit may include a memory controller circuit for communicating with an off-chip memory device. The memory controller is operable in a read-write major mode that is capable of dynamically adapting to any memory traffic pattern, which results in improved memory scheduling efficiency across different user applications. The memory controller may include at least a write command queue, a read command queue, an arbiter, and a command scheduler. The command scheduler may monitor a write command count, a read command count, a write stall count, and a read stall count to determine whether to dynamically adjust a read burst threshold setting and a write burst threshold setting.

公开(公告)号：US20190267062A1

公开(公告)日：2019-08-29

申请号：US16410956

申请日：2019-05-13

Applicant: Intel Corporation

Inventor： Tat Hin Tan ,  Chee Hak Teh ,  Tick Sern Loh ,  Wilfred Wee Kee King ,  Yu Ying Ong

IPC: G11C8/18 ,  H03K17/041

Abstract: An integrated circuit is operable to communicate with an external component. The integrated circuit may include driver circuits for outputting clock signals and associated control signals to the external component in accordance with a predetermined interface protocol. The clock signals may toggle more frequently than the associated control signals. To help mitigate potential transistor aging effects that could negatively impact timing margins for the control signals, the control signals may be periodically toggled even during idle periods as allowed by the predetermined interface protocol to help improve timing margins.

公开(公告)号：US20240296140A1

公开(公告)日：2024-09-05

申请号：US18662621

申请日：2024-05-13

Applicant: Intel Corporation

Inventor： Chee Hak Teh ,  Yu Ying Ong ,  George Chong Hean Ooi

IPC: G06F15/78 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F15/7825 ,  G06F13/1631 ,  G06F13/1673 ,  G06F13/4004

Abstract: Described herein are memory controllers for integrated circuits that implement network-on-chip (NoC) to provide access to memory to couple processing cores of the integrated circuit to a memory device. The NoC may be dedicated to service the memory controller and may include one or more routers to facilitate management of the access to the memory controller.

公开(公告)号：US11216397B2

公开(公告)日：2022-01-04

申请号：US16726132

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Lai Guan Tang ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Chee Hak Teh ,  Md Altaf Hossain

IPC: G06F13/20 ,  G06F13/40

Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.

公开(公告)号：US20190227590A1

公开(公告)日：2019-07-25

申请号：US16367925

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

IPC: G06F1/10 ,  H01L23/31

Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.

公开(公告)号：US20190214996A1

公开(公告)日：2019-07-11

申请号：US16351268

申请日：2019-03-12

Applicant: Intel Corporation

Inventor： Chang Kian Tan ,  Chee Hak Teh

IPC: H03K19/177 ,  G06F11/10 ,  G11C29/52 ,  G11C11/419 ,  G11C11/418

CPC classification number: H03K19/17744 ,  G06F11/1068 ,  G11C11/418 ,  G11C11/419 ,  G11C29/52 ,  H03K19/1776

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.