公开(公告)号：US11016549B2

公开(公告)日：2021-05-25

申请号：US15870629

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Poh Thiam Teoh ,  Mikal C. Hunsaker ,  Su Wei Lim ,  Gim Chong Lee ,  Hooi Kar Loo ,  Shashitheren Kerisnan ,  Siang Lin Tan ,  Ming Chew Lee ,  Ngeok Kuan Wai ,  Li Len Lim

IPC: G06F1/26 ,  G06F1/10 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.