公开(公告)号：US09646720B2

公开(公告)日：2017-05-09

申请号：US14813010

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Joon-Sung Yang ,  Darshan Kobla ,  Liwei Ju ,  David Zimmerman

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/04 ,  H01L21/66 ,  H01L25/065 ,  H01L23/48

CPC classification number: G11C29/70 ,  G11C29/025 ,  G11C29/04 ,  G11C29/4401 ,  G11C29/702 ,  G11C29/785 ,  G11C29/846 ,  G11C2213/71 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

公开(公告)号：US10224115B2

公开(公告)日：2019-03-05

申请号：US15589308

申请日：2017-05-08

Applicant: Intel Corporation

Inventor： Joon-Sung Yang ,  Darshan Kobla ,  Liwei Ju ,  David Zimmerman

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/04 ,  H01L21/66 ,  H01L25/065 ,  H01L23/48

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.

公开(公告)号：US20160055922A1

公开(公告)日：2016-02-25

申请号：US14813010

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Joon-Sung Yang ,  Darshan Kobla ,  Liwei Ju ,  David Zimmerman

IPC: G11C29/00 ,  G11C29/04

CPC classification number: G11C29/70 ,  G11C29/025 ,  G11C29/04 ,  G11C29/4401 ,  G11C29/702 ,  G11C29/785 ,  G11C29/846 ,  G11C2213/71 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.