公开(公告)号：US20210193547A1

公开(公告)日：2021-06-24

申请号：US16721802

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chandra Mohan JHA ,  Je-Young CHANG ,  Chia-Pin CHIU ,  Liwei WANG

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

公开(公告)号：US20210057381A1

公开(公告)日：2021-02-25

申请号：US16548255

申请日：2019-08-22

Applicant: Intel Corporation

Inventor： Xavier F. BRUN ,  Kaizad MISTRY ,  Paul R. START ,  Nisha ANANTHAKRISHNAN ,  Yawei LIANG ,  Jigneshkumar P. PATEL ,  Sairam AGRAHARAM ,  Liwei WANG

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.