公开(公告)号：US20220199503A1

公开(公告)日：2022-06-23

申请号：US17129846

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Manish DUBEY ,  Guruprasad ARAKERE ,  Deepak KULKARNI ,  Sairam AGRAHARAM ,  Wei-Lun K. JEN ,  Numair AHMED ,  Kousik GANESAN ,  Amol D. JADHAV ,  Kyu-Oh LEE

IPC: H01L23/498 ,  H01L21/48

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.

公开(公告)号：US20190043772A1

公开(公告)日：2019-02-07

申请号：US16075120

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Purushotham Kaushik MUTHUR SRINATH ,  Pramod MALATKAR ,  Sairam AGRAHARAM ,  Chandra M. JHA ,  Arnab CHOUDHURY ,  Nachiket R. RARAVIKAR

IPC: H01L23/26 ,  H01L23/433

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

公开(公告)号：US20240128256A1

公开(公告)日：2024-04-18

申请号：US18397891

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Robert L. SANKMAN ,  Sairam AGRAHARAM ,  Shengquan OU ,  Thomas J. DE BONIS ,  Todd SPENCER ,  Yang SUN ,  Guotao WANG

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/11013 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051

Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

公开(公告)号：US20230238339A1

公开(公告)日：2023-07-27

申请号：US18128954

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/538

CPC classification number: H01L23/585 ,  H01L23/5385 ,  H01L23/544

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20210057381A1

公开(公告)日：2021-02-25

申请号：US16548255

申请日：2019-08-22

Applicant: Intel Corporation

Inventor： Xavier F. BRUN ,  Kaizad MISTRY ,  Paul R. START ,  Nisha ANANTHAKRISHNAN ,  Yawei LIANG ,  Jigneshkumar P. PATEL ,  Sairam AGRAHARAM ,  Liwei WANG

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

公开(公告)号：US20220231007A1

公开(公告)日：2022-07-21

申请号：US17716934

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Robert L. SANKMAN ,  Sairam AGRAHARAM ,  Shengquan OU ,  Thomas J. DE BONIS ,  Todd SPENCER ,  Yang SUN ,  Guotao WANG

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18 ,  H01L21/56

Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

公开(公告)号：US20210125942A1

公开(公告)日：2021-04-29

申请号：US17143142

申请日：2021-01-06

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20200013734A1

公开(公告)日：2020-01-09

申请号：US16576520

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Dae-Woo KIM ,  Sujit SHARAN ,  Sairam AGRAHARAM

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US20250112174A1

公开(公告)日：2025-04-03

申请号：US18374618

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Siddarth KUMAR ,  Shripad GOKHALE ,  Edvin CETEGEN ,  Praneeth NAMPALLY ,  Astitva TRIPATHI ,  Sairam AGRAHARAM

IPC: H01L23/00 ,  H01L21/3205

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for forming an annealed shape metal alloy (SMA) on a wafer or a die complex. In embodiments, the annealed SMA, when heated above a transition temperature, may enter an Austenite phase and return to the shape that the wafer or die complex had when it was annealed. In embodiments, this may maintain a shape of a wafer or a die complex during higher temperature processing, for example during reflow, when the package undergoes fabrication. Other embodiments may be described and/or claimed.

公开(公告)号：US20230317653A1

公开(公告)日：2023-10-05

申请号：US17709367

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Xiaoxuan SUN ,  Amey Anant APTE ,  Dingying David XU ,  Sairam AGRAHARAM ,  Gang DUAN ,  Ashay DANI

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/80379 ,  H01L2224/8049 ,  H01L2924/07025 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/13025 ,  H01L24/13 ,  H01L24/03 ,  H01L2224/03845 ,  H01L2224/94 ,  H01L24/94 ,  H01L2224/80855 ,  H01L2224/80201 ,  H01L2225/1023 ,  H01L2225/1047

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.