公开(公告)号：US20220199482A1

公开(公告)日：2022-06-23

申请号：US17131671

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Chia-Pin CHIU ,  Zhimin WAN ,  Peng LI ,  Deepak GOYAL

IPC: H01L23/367 ,  H01L23/40 ,  H01L23/38

Abstract: Embodiments disclosed herein include thermoelectric cooling (TEC) dies for multi-chip packages. In an embodiment, a TEC die comprises a glass substrate and an array of N-type semiconductor vias and P-type semiconductor vias through the glass substrate. In an embodiment, conductive traces are over the glass substrate, and individual ones of the conductive traces connect an individual one of the N-type semiconductor vias to an individual one of the P-type semiconductor vias.

公开(公告)号：US20240282667A1

公开(公告)日：2024-08-22

申请号：US18635894

申请日：2024-04-15

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20210257277A1

公开(公告)日：2021-08-19

申请号：US16794789

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20210193552A1

公开(公告)日：2021-06-24

申请号：US16721809

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Jin YANG ,  Chia-Pin CHIU ,  Peng LI ,  Deepak GOYAL

IPC: H01L23/367 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31

Abstract: Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.

公开(公告)号：US20210249324A1

公开(公告)日：2021-08-12

申请号：US16783819

申请日：2020-02-06

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chia-Pin CHIU ,  Chandra Mohan JHA

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

公开(公告)号：US20210193548A1

公开(公告)日：2021-06-24

申请号：US16721807

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chia-Pin CHIU ,  Peng LI ,  Shankar DEVASENATHIPATHY

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

公开(公告)号：US20210193547A1

公开(公告)日：2021-06-24

申请号：US16721802

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chandra Mohan JHA ,  Je-Young CHANG ,  Chia-Pin CHIU ,  Liwei WANG

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first, second, and third microelectronic devices on a package substrate. The first microelectronic device has a top surface substantially coplanar to a top surface of the second microelectronic device. The third microelectronic device has a top surface above the top surfaces of the first and second microelectronic devices. The semiconductor package includes a first conductive layer on the first and second microelectronic devices, and a second conductive layer on the third microelectronic device. The second conductive layer has a thickness less than a thickness of the first conductive layer, and a top surface substantially coplanar to a top surface of the first conductive layer. The semiconductor includes thermal interface materials on the first and second conductive layers. The first and second conductive layers are comprised of copper, silver, boron nitride, or graphene.

公开(公告)号：US20230128903A1

公开(公告)日：2023-04-27

申请号：US18088478

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20210118756A1

公开(公告)日：2021-04-22

申请号：US16659395

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chandra Mohan JHA ,  Je-Young CHANG ,  Chia-Pin CHIU

IPC: H01L23/15 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a hybrid interposer with a first region and a second region. The first region is comprised of glass or low thermal conductive materials, and the second region is comprised of silicon or diamond materials. The semiconductor package includes a first die on the first region of the hybrid interposer, a second die on the second region of the hybrid interposer, and an integrated heat spreader over the first die, the second die, and the hybrid interposer. The hybrid interposer includes first and second interconnects, where the first interconnects vertically extend from a bottom surface of the first region to a top surface of the first region, and where the second interconnects vertically extend from a bottom surface of the second region to a top surface of the second region. The first interconnects are through-glass vias, and the second interconnects are through-silicon vias.