公开(公告)号：US11954360B2

公开(公告)日：2024-04-09

申请号：US17009241

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Narasimha Lanka ,  Kuljit Bains ,  Lohit Yerva

IPC: G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06N20/00

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/0679 ,  G06F11/1004 ,  G06F13/1668 ,  G06N20/00

Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.