公开(公告)号：US20200185052A1

公开(公告)日：2020-06-11

申请号：US16795119

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit Bains ,  Wei Chen ,  Rajat Agarwal

IPC: G11C29/00 ,  G11C29/44 ,  G11C11/406 ,  G11C7/10

Abstract: An embodiment of an electronic memory apparatus may include storage media, and logic communicatively coupled to the storage media, the logic to determine if a mode is set to one of a first mode or a second mode, perform a soft post package repair in the first mode, and undo the soft post package repair in the second mode. Other embodiments are disclosed and claimed.

公开(公告)号：US20200251159A1

公开(公告)日：2020-08-06

申请号：US16854280

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Narasimha Lanka ,  Kuljit Bains ,  Lakshmipriya Seshan

IPC: G11C11/4063 ,  H01L27/108 ,  H01L27/06 ,  H01L23/538 ,  G11C5/06

Abstract: An embodiment of a memory apparatus may include a memory core, a plurality of through-silicon vias (TSVs), and data bus inversion logic coupled between the memory core and the TSVs to encode and decode a data signal on a signal path through the TSVs in accordance with a data bus inversion of the data signal. Other embodiments are disclosed and claimed.

公开(公告)号：US09824743B2

公开(公告)日：2017-11-21

申请号：US15585678

申请日：2017-05-03

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Kuljit Bains ,  John Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

公开(公告)号：US11954360B2

公开(公告)日：2024-04-09

申请号：US17009241

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Narasimha Lanka ,  Kuljit Bains ,  Lohit Yerva

IPC: G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06N20/00

CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/0679 ,  G06F11/1004 ,  G06F13/1668 ,  G06N20/00

Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.

公开(公告)号：US20230086101A1

公开(公告)日：2023-03-23

申请号：US18057476

申请日：2022-11-21

Applicant: Intel Corporation

Inventor： Cong Li ,  Kuljit Bains ,  Shen Zhou

IPC: G06F11/10 ,  G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that identifies a plurality of fully correctable patterns associated with an error correction code (ECC) in a memory controller, detects one or more correctable errors in a memory module coupled to the memory controller, and generates an alert if an error-bit pattern of the one or more correctable errors does not match one or more of the plurality of fully correctable patterns.