公开(公告)号：US20230119525A1

公开(公告)日：2023-04-20

申请号：US17503408

申请日：2021-10-18

Applicant: Intel Corporation

Inventor： Loke Yip FOO ,  Teong Guan YEW ,  Bok Eng CHEAH

IPC: H01L23/498 ,  H01L25/16 ,  H01L21/48

Abstract: The present disclosure is directed generally to semiconductor packages, semiconductor package substrates, and methods for making them, which include packages substrates with embedded passive devices positioned between plated through hole vias configured for an improved power delivery network.

公开(公告)号：US20220077070A1

公开(公告)日：2022-03-10

申请号：US17090933

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Choong Kooi CHEE ,  Bok Eng CHEAH ,  Teong Guan YEW ,  Jackson Chung Peng KONG ,  Loke Yip FOO

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/13 ,  H01L21/56 ,  H01L21/48

Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.

公开(公告)号：US20240063148A1

公开(公告)日：2024-02-22

申请号：US17889395

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Loke Yip FOO ,  Teong Guan YEW ,  Bok Eng CHEAH

IPC: H01L23/64 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/642 ,  H01L23/5381 ,  H01L23/5386 ,  H01L21/4846

Abstract: A device is provided, including a bridge substrate and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each of the plurality of trenches may include a conductive filling; a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer; a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer; and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the conductive fillings of the plurality of trenches.

公开(公告)号：US20230137035A1

公开(公告)日：2023-05-04

申请号：US18089207

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Loke Yip FOO ,  Choong Kooi CHEE

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US20220078914A1

公开(公告)日：2022-03-10

申请号：US17089736

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Loke Yip FOO ,  Choong Kooi CHEE ,  Teong Guan YEW

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H05K3/32 ,  H05K3/34

Abstract: A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.