公开(公告)号：US20170069597A1

公开(公告)日：2017-03-09

申请号：US15122382

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  M. Clair WEBB ,  Patrick MORROW ,  Kimin JUN

IPC: H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538

Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

Abstract translation: 一种方法，包括在衬底上形成多个第一器件和多个第一互连件; 将包括多个第二设备的第二设备层耦合到所述多个第一互连中的一个，并且在所述第二设备层上形成多个第二互连。 一种包括第一装置层的装置，包括设置在多个第一互连和多个第二互连之间的多个第一电路装置和包括多个第二装置的第二装置层，所述第二装置层并置并耦合到所述多个第一互连中的一个， 所述多个第二互连，其中所述多个第一装置和所述多个第二装置中的一个包括具有比所述多个第一装置和所述多个第二装置中的另一个更高的电压范围的装置。

公开(公告)号：US20240362391A1

公开(公告)日：2024-10-31

申请号：US18769148

申请日：2024-07-10

Applicant: Intel Corporation

Inventor： Ranjith KUMAR ,  Quan SHI ,  Mark T. BOHR ,  Andrew W. YEOH ,  Sourav CHAKRAVARTY ,  Barbara A. CHAPPELL ,  M. Clair WEBB

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/337 ,  G06F30/347 ,  G06F30/373 ,  G06F30/3947 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118

CPC classification number: G06F30/392 ,  G06F30/337 ,  G06F30/347 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  G06F30/20 ,  G06F30/373 ,  G06F30/3947 ,  H01L2027/11875

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US20220149075A1

公开(公告)日：2022-05-12

申请号：US17585101

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Ranjith KUMAR ,  Quan SHI ,  Mark T. BOHR ,  Andrew W. YEOH ,  Sourav CHAKRAVARTY ,  Barbara A. CHAPPELL ,  M. Clair WEBB

IPC: H01L27/118 ,  G06F30/392 ,  H01L27/02 ,  H01L27/092

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.