公开(公告)号：US20210263880A1

公开(公告)日：2021-08-26

申请号：US16799192

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Mahesh Krishnappayya Kumashikar ,  Srikanth Nimmagadda

IPC: G06F13/42 ,  G06F9/38 ,  G06F13/40

Abstract: Embodiments may relate to a die with a processor. The die may include a first input/output (I/O) tile adjacent to a first side of the processor, and a second I/O tile adjacent to a second side of the processor. The first or second I/O tiles may be communicatively coupled with the processor. Other embodiments may be described or claimed.

公开(公告)号：US20240232122A1

公开(公告)日：2024-07-11

申请号：US18613256

申请日：2024-03-22

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Mahesh Krishnappayya Kumashikar ,  Srikanth Nimmagadda

IPC: G06F13/42 ,  G06F9/38 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F9/3822 ,  G06F9/3869 ,  G06F9/3877 ,  G06F13/4027

Abstract: Embodiments may relate to a microelectronic assembly including a substrate; a first die electrically coupled to the substrate, wherein the first die includes a first edge, a second edge, a third edge opposite the first edge, and a fourth edge opposite the second edge; and a second die electrically coupled to the substrate adjacent to the second edge of the first die and communicatively coupled to the first die, wherein the second die includes a fifth edge and a sixth edge opposite the fifth edge, and wherein the fifth edge of the second die is substantially aligned with the first edge of the first die and the sixth edge of the second die extends beyond the third edge of the first die, where the first die includes a processor die and the second die includes an input/output (I/O) die.