公开(公告)号：US20220209959A1

公开(公告)日：2022-06-30

申请号：US17134352

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Siddhartha CHHABRA ,  Manjula PEDDIREDDY ,  Hormuzd KHOSRAVI

IPC: H04L9/32 ,  H04L9/08 ,  G06F12/14 ,  G06F13/16

Abstract: In embodiments detailed herein describe an encryption architecture with fast zero support (e.g., FZ-MKTME) to allow memory encryption and integrity architecture to work efficiently with 3DXP or other far memory memories. In particular, an encryption engine for the purpose of fast zeroing in the far memory controller is detailed along with mechanisms for consistent key programming of this engine. For example, an instruction is detailed which allows software to send keys protected even when the controller is located outside of a system on a chip (SoC), etc.

公开(公告)号：US20220207190A1

公开(公告)日：2022-06-30

申请号：US17134344

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Siddhartha CHHABRA ,  Manjula PEDDIREDDY ,  Rajat AGARWAL

IPC: G06F21/79 ,  G06F21/60 ,  G11C29/42

Abstract: Techniques for Scalable Memory Integrity and Enhanced Reliability, Availability, and Serviceability (SMIRAS) based systems are described. A SMIRAS based system may be enabled to use an integrity-based metadata organization that stores data, metadata, and a first portion of ECC data together in memory and a second portion of ECC data in sequestered memory; or using a compression based organization that stores compressed data, compression metadata, and an second portion of ECC data as a cacheline.