公开(公告)号：US20250113529A1

公开(公告)日：2025-04-03

申请号：US18375082

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Jessica PANELLA ,  Manjunath CHINNAPPAMUDALIAR RAJAGOPAL ,  SHARANYA SUBRAMANIAM ,  Robert JOACHIM ,  Dario FARIAS

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having fin cuts, and methods of fabricating integrated circuit structures having fin cuts, are described. For example, an integrated circuit structure includes a first fin structure or nanowire stack and sub-fin pairing separated from a second fin structure or nanowire stack and sub-fin pairing by a cut, wherein an end of the first fin structure or nanowire stack and sub-fin pairing is facing toward an end of the second fin structure or nanowire stack and sub-fin pairing. A first gate structure is overlying the first fin structure or nanowire stack and sub-fin pairing, and a second gate structure is overlying the second fin structure or nanowire stack and sub-fin pairing. A first isolation structure is overlying the end of the first fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the first gate structure, and a second isolation structure is overlying the end of the second fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the second gate structure.