公开(公告)号：US20240105774A1

公开(公告)日：2024-03-28

申请号：US17955513

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Jessica PANELLA ,  Saurabh ACHARYA ,  Desalegne B. TEWELDEBRHAN ,  Madeleine BEASLEY

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Integrated circuit structures having uniform epitaxial source or drain cut are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires. A second sub-fin structure is beneath a second stack of nanowires. A first epitaxial source or drain structure is at an end of the first stack of nanowires, the first epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall. A second epitaxial source or drain structure is at an end of the second stack of nanowires, the second epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall, the first lateral sidewall of the second epitaxial source or drain structure laterally spaced apart from the second lateral sidewall of the first epitaxial source or drain structure.

公开(公告)号：US20250113529A1

公开(公告)日：2025-04-03

申请号：US18375082

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Jessica PANELLA ,  Manjunath CHINNAPPAMUDALIAR RAJAGOPAL ,  SHARANYA SUBRAMANIAM ,  Robert JOACHIM ,  Dario FARIAS

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having fin cuts, and methods of fabricating integrated circuit structures having fin cuts, are described. For example, an integrated circuit structure includes a first fin structure or nanowire stack and sub-fin pairing separated from a second fin structure or nanowire stack and sub-fin pairing by a cut, wherein an end of the first fin structure or nanowire stack and sub-fin pairing is facing toward an end of the second fin structure or nanowire stack and sub-fin pairing. A first gate structure is overlying the first fin structure or nanowire stack and sub-fin pairing, and a second gate structure is overlying the second fin structure or nanowire stack and sub-fin pairing. A first isolation structure is overlying the end of the first fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the first gate structure, and a second isolation structure is overlying the end of the second fin structure or nanowire stack and sub-fin pairing and laterally spaced apart from the second gate structure.

公开(公告)号：US20250006740A1

公开(公告)日：2025-01-02

申请号：US18216325

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vivek VISHWAKARMA ,  Jessica PANELLA ,  Sean PURSEL ,  Dincer UNLUER ,  Shaun MILLS ,  Hongqian SUN ,  Charles H. WALLACE

IPC: H01L27/12 ,  H01L21/84

Abstract: Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.