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公开(公告)号:US11211934B2
公开(公告)日:2021-12-28
申请号:US17028923
申请日:2020-09-22
Applicant: Intel Corporation
Inventor: Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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公开(公告)号:US20190296747A1
公开(公告)日:2019-09-26
申请号:US15933235
申请日:2018-03-22
Applicant: Intel Corporation
Inventor: Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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公开(公告)号:US20210083678A1
公开(公告)日:2021-03-18
申请号:US17028923
申请日:2020-09-22
Applicant: Intel Corporation
Inventor: Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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公开(公告)号:US20170324415A1
公开(公告)日:2017-11-09
申请号:US15146483
申请日:2016-05-04
Applicant: Intel Corporation
Inventor: Mark L. Neidengard
IPC: H03K23/00
CPC classification number: H03K23/005 , H03M7/16
Abstract: Apparatuses, systems and methods associated with bidirectional Gray code counter design are disclosed herein. In embodiments, a bidirectional Gray code counter may include a sequential logic element to store a Gray code value and logic circuitry. The logic circuitry may be to determine, based on a bidirectional indicator signal, whether to increment or decrement the Gray code value update, through performance of an increment or a decrement of the Gray code value based on the determination of whether to increment or decrement the Gray code value, the Gray code value to be a sequential Gray code value and replace the Gray code value stored in the sequential logic element with the updated Gray code value. Other embodiments may be described and/or claimed.
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公开(公告)号:US10790832B2
公开(公告)日:2020-09-29
申请号:US15933235
申请日:2018-03-22
Applicant: Intel Corporation
Inventor: Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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公开(公告)号:US10439617B2
公开(公告)日:2019-10-08
申请号:US15146483
申请日:2016-05-04
Applicant: Intel Corporation
Inventor: Mark L. Neidengard
Abstract: Apparatuses, systems and methods associated with bidirectional Gray code counter design are disclosed herein. In embodiments, a bidirectional Gray code counter may include a sequential logic element to store a Gray code value and logic circuitry. The logic circuitry may be to determine, based on a bidirectional indicator signal, whether to increment or decrement the Gray code value update, through performance of an increment or a decrement of the Gray code value based on the determination of whether to increment or decrement the Gray code value, the Gray code value to be a sequential Gray code value and replace the Gray code value stored in the sequential logic element with the updated Gray code value. Other embodiments may be described and/or claimed.
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