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公开(公告)号：US10790838B1
公开(公告)日：2020-09-29
申请号：US16412165
申请日：2019-05-14
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Vaughn J. Grossnickle , Syed Feruz Syed Farooq , Mark Neidengard , Nasser A. Kurd
Abstract: Dynamic voltage frequency scaling to transition to a target clock frequency and associated target voltage is provided. Dynamic voltage frequency scaling to a different clock frequency is performed by gradually changing the clock frequency using discrete variable-size steps, while dynamically switching to faster or slower reference clock frequencies as appropriate to harmonize the frequency trajectory with system requirements.
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公开(公告)号：US20210083678A1
公开(公告)日：2021-03-18
申请号：US17028923
申请日：2020-09-22
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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公开(公告)号：US10423182B2
公开(公告)日：2019-09-24
申请号：US15478457
申请日：2017-04-04
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Gerhard Schrom , Vaughn J. Grossnickle , Nasser A. Kurd
IPC: G05F1/625 , H03L7/093 , H03K5/24 , G01R19/165
Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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公开(公告)号：US10790832B2
公开(公告)日：2020-09-29
申请号：US15933235
申请日：2018-03-22
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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公开(公告)号：US20200004286A1
公开(公告)日：2020-01-02
申请号：US16566368
申请日：2019-09-10
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Gerhard Schrom , Vaughn J. Grossnickle , Nasser A. Kurd
IPC: G05F1/625 , H03L7/093 , H03K5/24 , G01R19/165
Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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Patent Agency Ranking
公开(公告)号：US20180284828A1
公开(公告)日：2018-10-04
申请号：US15478457
申请日：2017-04-04
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Gerhard Schrom , Vaughn J. Grossnickle , Nasser A. Kurd
IPC: G05F1/625 , H03L7/093 , H03K5/24 , G01R19/165
CPC classification number: G05F1/625 , G01R19/16552 , H03K5/24 , H03L7/06
Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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公开(公告)号：US11211934B2
公开(公告)日：2021-12-28
申请号：US17028923
申请日：2020-09-22
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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公开(公告)号：US11048284B2
公开(公告)日：2021-06-29
申请号：US16566368
申请日：2019-09-10
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Gerhard Schrom , Vaughn J. Grossnickle , Nasser A. Kurd
IPC: G05F1/625 , G01R19/165 , H03K5/24 , H03L7/093 , H03L7/06
Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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公开(公告)号：US20200005728A1
公开(公告)日：2020-01-02
申请号：US16019924
申请日：2018-06-27
Applicant: Intel Corporation
Inventor： Nasser Kurd , Daniel Ragland , Ameya Ambardekar , John Fallin , Praveen Mosalikanti , Vaughn J. Grossnickle
Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.
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公开(公告)号：US20190296747A1
公开(公告)日：2019-09-26
申请号：US15933235
申请日：2018-03-22
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Qi Wang , Mark L. Neidengard , Vaughn J. Grossnickle , Nasser A. Kurd
Abstract: An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
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