公开(公告)号：US20180122744A1

公开(公告)日：2018-05-03

申请号：US15723083

申请日：2017-10-02

Applicant: Intel Corporation

Inventor： Ruth A. BRAIN ,  Kevin J. FISCHER ,  Michael A. CHILDS

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.