公开(公告)号：US20200090992A1

公开(公告)日：2020-03-19

申请号：US16582923

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Yuriy V. SHUSTERMAN ,  Flavio GRIGGIO ,  Tejaswi K. INDUKURI ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/528

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US20190221478A1

公开(公告)日：2019-07-18

申请号：US16249593

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Yuriy V. SHUSTERMAN ,  Flavio GRIGGIO ,  Tejaswi K. INDUKURI ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/76847 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US20200279069A1

公开(公告)日：2020-09-03

申请号：US16649588

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Ranjith KUMAR ,  Mark T. BOHR ,  Ruth A. BRAIN ,  Marni NABORS ,  Tai-Hsuan WU ,  Sourav CHAKRAVARTY

IPC: G06F30/3953 ,  H01L23/50 ,  H01L23/522

Abstract: An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

公开(公告)号：US20190206728A1

公开(公告)日：2019-07-04

申请号：US16329172

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Marvin Y. PAIK ,  Hyunsoo PARK ,  Mohit K. HARAN ,  Alexander F. KAPLAN ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528

Abstract: Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.

公开(公告)号：US20220068707A1

公开(公告)日：2022-03-03

申请号：US17521753

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Marvin Y. PAIK ,  Hyunsoo PARK ,  Mohit K. HARAN ,  Alexander F. KAPLAN ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in a trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.

公开(公告)号：US20190013353A1

公开(公告)日：2019-01-10

申请号：US16067801

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Oleg GOLONZKA ,  Tahir GHANI ,  Ruth A. BRAIN ,  Yih WANG

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L23/532 ,  G11C11/16 ,  H01L23/522

Abstract: Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region including metal line/via pairings disposed in a dielectric layer disposed above a substrate. The logic processor also includes a spin torque transfer magnetoresistive random access memory (STT-MRAM) array including a plurality of magnetic tunnel junctions (MTJs). The MTJs are disposed in the dielectric layer.

公开(公告)号：US20180122744A1

公开(公告)日：2018-05-03

申请号：US15723083

申请日：2017-10-02

Applicant: Intel Corporation

Inventor： Ruth A. BRAIN ,  Kevin J. FISCHER ,  Michael A. CHILDS

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

公开(公告)号：US20170330761A1

公开(公告)日：2017-11-16

申请号：US15528736

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jasmeet S. CHAWLA ,  Ruth A. BRAIN ,  Richard E. SCHENKER ,  Kanwal Jit SINGH ,  Alan M. MEYERS

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/48 ,  H01L23/522

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/485 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2224/16225

Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.