公开(公告)号：US12148747B2

公开(公告)日：2024-11-19

申请号：US17033513

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Pratik Koirala ,  Nicole K. Thomas ,  Paul B. Fischer ,  Adel A. Elsherbini ,  Tushar Talukdar ,  Johanna M. Swan ,  Wilfred Gomes ,  Robert S. Chau ,  Beomseok Choi

IPC: H01L27/06 ,  H01L21/765 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：US20240204091A1

公开(公告)日：2024-06-20

申请号：US18084438

申请日：2022-12-19

Applicant: Intel Corporation

Inventor： Heli Vora ,  Marko Radosavljevic ,  Pratik Koirala ,  Han Wui Then ,  Michael Beumer ,  Ahmad Zubair ,  Samuel Bader

IPC: H01L29/778 ,  H01L21/285 ,  H01L21/306 ,  H01L29/20 ,  H01L29/47 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/28581 ,  H01L21/30621 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66462

Abstract: Devices, transistor structures, systems, and techniques are described herein related to low aluminum concentration aluminum gallium nitride interlayers for group III-nitride enhancement mode transistors. The low aluminum concentration aluminum gallium nitride interlayer includes a lower aluminum concentration than a polarization layer of the transistor, such that the polarization layer induces a two-dimensional electron gas in a semiconductor layer of the transistor. The low aluminum concentration aluminum gallium nitride interlayer may be implemented as an etch stop layer, as a gate liner, or both.