公开(公告)号：US20190004938A1

公开(公告)日：2019-01-03

申请号：US15640522

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Umberto Siciliani ,  Giulio Giuseppe Marotta ,  Tommaso Vali ,  Luca De Santis ,  Agostino Macerola ,  Violante Moshciano ,  Luigi Pilolli ,  Giovanni Santin ,  Michele Incarnati

IPC: G06F12/02 ,  G06F12/0802 ,  G06F12/04 ,  G06F12/1009 ,  G11C16/06 ,  G11C11/56

Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.

公开(公告)号：US11061762B2

公开(公告)日：2021-07-13

申请号：US16267323

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Naveen Prabhu Vittal Prabhu ,  Bharat M. Pathak ,  Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  Violante Moschiano ,  Walter Di Francesco ,  Michele Incarnati ,  Antonino Giuseppe La Spina

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C29/52 ,  G11C11/56 ,  G06F11/07 ,  G11C16/10 ,  G11C29/04

Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

公开(公告)号：US10922220B2

公开(公告)日：2021-02-16

申请号：US15640522

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Umberto Siciliani ,  Giulio Giuseppe Marotta ,  Tommaso Vali ,  Luca De Santis ,  Agostino Macerola ,  Violante Moshciano ,  Luigi Pilolli ,  Giovanni Santin ,  Michele Incarnati

IPC: G06F12/02 ,  G06F12/0802 ,  G06F12/04 ,  G06F12/1009 ,  G11C16/06 ,  G11C11/56 ,  G11C16/26 ,  G11C16/10

Abstract: Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can receive a page of data. The memory controller can segment the page of data into a group of data segments. The memory controller can program the group of data segments to memory cells in the plurality of memory cells that are associated with an inhibit tile group (ITG). The group of data segments for the page of data can be programmed using all bits included in each of the memory cells associated with the ITG.