公开(公告)号：US11954501B2

公开(公告)日：2024-04-09

申请号：US17697801

申请日：2022-03-17

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Bhavana Shankarappa ,  Kiran Mahesh Eriki

IPC: G06F9/44 ,  G06F9/4401

CPC classification number: G06F9/4411

Abstract: A scheme for restoring a password-protected endpoint device (e.g., a memory device) of a computer system to an operational state from a low power state without requiring user input of a device password. A password received for unlocking the device during a boot process is stored in a secure memory. The password-protected endpoint device subsequently enters the low power state, causing it to lock. During a transition from the low power state to an operational state, it is detected that the password for the endpoint device is stored in the secure memory. The password is fetched from the secure memory and used to unlock the endpoint device, thereby restoring the endpoint device to an operational state.

公开(公告)号：US20200225994A1

公开(公告)日：2020-07-16

申请号：US16832372

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Murali R. Iyengar ,  Karunakara Kotary ,  Ovais Pir ,  Sagar C. Pawar ,  Prakash Pillai ,  Raghavendra N. ,  Aneesh A. Tuljapurkar

IPC: G06F9/50 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/1009 ,  G06T1/60

Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.

公开(公告)号：US11922172B2

公开(公告)日：2024-03-05

申请号：US17028315

申请日：2020-09-22

Applicant: Intel Corporation

Inventor： Karunakara Kotary ,  Pannerkumar Rajagopal ,  Satish Muthiyalu ,  Rajesh Poornachandran

IPC: G06F9/4401 ,  G06F1/3212 ,  G06F9/445 ,  G06F9/451 ,  G06F11/30 ,  G06F11/34 ,  G06F12/0873 ,  G06F13/16 ,  G06F13/40 ,  G11C11/406

CPC classification number: G06F9/4403 ,  G06F1/3212 ,  G06F9/44505 ,  G06F9/451 ,  G06F11/3037 ,  G06F11/3409 ,  G06F12/0873 ,  G06F13/1668 ,  G06F13/4081 ,  G11C11/40622

Abstract: Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.

公开(公告)号：US20230342234A1

公开(公告)日：2023-10-26

申请号：US17724811

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Santhosh Raghuram Krishnaswamy ,  Siddhartha Selvaraj ,  Anshul Soni ,  Toby Zimmerman

IPC: G06F11/07 ,  G06F9/4401

CPC classification number: G06F11/0766 ,  G06F9/4406 ,  G06F11/0721

Abstract: The technology describe herein includes upon entering a mode of a processor that is not visible to an operating system (OS), setting a flag indicating entry into the mode and saving an identifier (ID) of an error causing entry into the mode; and responsive to a system reset initiation while in the mode, booting a basic input/output system (BIOS), creating an error record to be accessible to the OS after booting, the error record including the flag and the error ID, and booting the OS.

公开(公告)号：US11429289B2

公开(公告)日：2022-08-30

申请号：US16832125

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Karunakara Kotary ,  Pannerkumar Rajagopal ,  Sahil Dureja ,  Mohamed Haniffa ,  Prashant Dewan

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/4401

Abstract: An apparatus to facilitate memory map security in a system on chip (SOC), is disclosed. The apparatus includes a micro controller to receive a request to grant a host device an access to a memory device and perform an alias checking process to verify accuracy of a memory map of the memory device.

公开(公告)号：US20220215099A1

公开(公告)日：2022-07-07

申请号：US17705747

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Sriram Ranganathan ,  Pannerkumar Rajagopal ,  Saravanakumar Ulaganathan ,  Siddhartha Selvaraj ,  Radhakrishna Pai

IPC: G06F21/57 ,  G06F15/78

Abstract: The disclosure generally relates method, system and apparatus to prevent denial of service (DOS) attacks on PCIe based computing devices. In an exemplary embodiment, an independent register is used in combination with a filter driver and additional logic to form an integrity check for power down instructions. An exemplary system includes a register circuitry corresponding to the IP device, the register circuitry having a designated storage bit to indicate an unlocked state of the register; a filter driver to receive a first power state transition request when the IP device is idle after a predetermined period, the power state transition request defining a timeout period; a controller to change the power state of the IP device to the unlock state; a decision logic to receive and authenticate a second power state transition request in response to validation of register circuitry being unlocked.

公开(公告)号：US20210373833A1

公开(公告)日：2021-12-02

申请号：US16890798

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Sagar Pawar ,  Prakash Pillai ,  Ovais Pir ,  Murali Iyengar ,  Pannerkumar Rajagopal ,  Raghavendra N ,  Aneesh Tuljapurkar

IPC: G06F3/14 ,  G06F3/0487 ,  G09G3/34

Abstract: Techniques and mechanisms for power management of display devices based on an indication that a user exhibits interest in one, but not all, of said display devices. In an embodiment, logic of a computer device identifies a condition wherein a user of the computer device exhibits insufficient interest in a first display device, while exhibiting at least some interest user in a second display device. The first display device and the second display device support an extended display mode of an operating system. Based on the condition, the logic automatically reduces a consumption of power by the first display device. Of the first display device and the second display device, only the first display device is subjected to a power state transition based on the condition.

公开(公告)号：US12007823B2

公开(公告)日：2024-06-11

申请号：US17702504

申请日：2022-03-23

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Raghavendra N ,  Ovais Pir ,  Prakash Pillai ,  Sagar C. Pawar

IPC: G06F1/32 ,  G06F1/3231

CPC classification number: G06F1/3231

Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

公开(公告)号：US20240004454A1

公开(公告)日：2024-01-04

申请号：US17809652

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sagar C. Pawar ,  Pannerkumar Rajagopal ,  Raghavendra Nagaraj ,  Ovais F. Pir ,  Prakash Pillai

IPC: G06F1/3296 ,  G06F1/30

CPC classification number: G06F1/3296 ,  G06F1/30

Abstract: In an embodiment, a processor may include processing circuits to execute instructions. The processor may also include at least one circuit to: detect a management mode trigger event during operation of the processor in a first power state, the management mode trigger event to initiate a management mode in the processor; in response to a detection of the management mode trigger event, switch the processor from the first power state to a second power state; and after a switch of the processor from the first power state to the second power state, initiate the management mode in the processor. Other embodiments are described and claimed.

公开(公告)号：US11720401B2

公开(公告)日：2023-08-08

申请号：US16832372

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Pannerkumar Rajagopal ,  Murali R Iyengar ,  Karunakara Kotary ,  Ovais Pir ,  Sagar C Pawar ,  Prakash Pillai ,  Raghavendra N ,  Aneesh A Tuljapurkar

IPC: G06F9/4401 ,  G06F9/50 ,  G06F9/54 ,  G06F12/1009 ,  G06T1/60

CPC classification number: G06F9/5016 ,  G06F9/4406 ,  G06F9/544 ,  G06F12/1009 ,  G06T1/60

Abstract: Described is a system where memory can be allocated for use by an adapter pre-boot and preserved for use post-boot. A BIOS can allocate for pre-boot hardware operations (e.g., graphics drivers, framebuffers, etc.) and mark this allocated memory as preserved. An indication of the allocated memory can be provided for an OS, such that post-boot, the OS can reclaim and reallocate this memory.