公开(公告)号：US20250068588A1

公开(公告)日：2025-02-27

申请号：US18822815

申请日：2024-09-03

Applicant: Intel Corporation

Inventor： Joydeep RAY ,  Aravindh ANANTARAMAN ,  Abhishek R. APPU ,  Altug KOKER ,  Elmoustapha OULD-AHMED-VALL ,  Valentin ANDREI ,  Subramaniam MAIYURAN ,  Nicolas GALOPPO VON BORRIES ,  Varghese GEORGE ,  Mike MACPHERSON ,  Ben ASHBAUGH ,  Murali RAMADOSS ,  Vikranth VEMULAPALLI ,  William SADLER ,  Jonathan PEARCE ,  Sungye KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240045830A1

公开(公告)日：2024-02-08

申请号：US18450685

申请日：2023-08-16

Applicant: Intel Corporation

Inventor： Joydeep RAY ,  Aravindh ANANTARAMAN ,  Abhishek R. APPU ,  Altug KOKER ,  Elmoustapha OULD-AHMED-VALL ,  Valentin ANDREI ,  Subramaniam MAIYURAN ,  Nicolas GALOPPO VON BORRIES ,  Varghese GEORGE ,  Mike MACPHERSON ,  Ben ASHBAUGH ,  Murali RAMADOSS ,  Vikranth VEMULAPALLI ,  William SADLER ,  Jonathan PEARCE ,  Sungye KIM

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

CPC classification number: G06F15/8069 ,  G06F9/30163 ,  G06F9/3877 ,  G06T15/005 ,  G06F9/3836

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.