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1.
公开(公告)号:US20200334149A1
公开(公告)日:2020-10-22
申请号:US16843380
申请日:2020-04-08
Applicant: Intel Corporation
Inventor: Mohamed ARAFA , Raj K. RAMANUJAN
IPC: G06F12/0804 , G06F12/12 , G06F12/02 , G06F12/0866
Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.
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2.
公开(公告)号:US20220334968A1
公开(公告)日:2022-10-20
申请号:US17856947
申请日:2022-07-01
Applicant: Intel Corporation
Inventor: Mohamed ARAFA , Raj K. RAMANUJAN
IPC: G06F12/0804 , G06F12/12 , G06F12/02 , G06F12/0866
Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.
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3.
公开(公告)号:US20190042420A1
公开(公告)日:2019-02-07
申请号:US16102604
申请日:2018-08-13
Applicant: Intel Corporation
Inventor: Mohamed ARAFA , Raj K. RAMANUJAN
IPC: G06F12/0804 , G06F12/0866 , G06F12/12 , G06F12/02
Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.
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公开(公告)号:US20210103684A1
公开(公告)日:2021-04-08
申请号:US17123592
申请日:2020-12-16
Applicant: Intel Corporation
Inventor: Shamanna M. DATTA , Asher M. ALTMAN , John K. GROOMS , Mohamed ARAFA
Abstract: Techniques for tamper detection of a memory module having non-volatile memory devices resident on a printed circuit board (PCB) by circuitry of a controller also resident on the PCB. Examples include determining resistance values of a character pattern sprayed on a side of a cover facing the non-volatile memory devices using conductive ink following first and second boots of the memory module and asserting a bit of a register to indicate tampering of the memory modules based on a comparison of the resistance values. Tamper policy actions may be initiated based on detection of tampering.
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5.
公开(公告)号:US20190034337A1
公开(公告)日:2019-01-31
申请号:US15857463
申请日:2017-12-28
Applicant: Intel Corporation
Inventor: Mohamed ARAFA , Krishnaswamy VISWANATHAN
IPC: G06F12/0811 , G06F12/02 , G06F12/0815 , G06F12/0864
Abstract: A method is described. The method includes recognizing higher priority users of a multi-level system memory characterized by a faster higher level and a slower lower level in which the higher level is to act as a cache for the lower level and in which a first capacity of the higher level is less than a second capacity of the lower level such that caching resources of the higher level are oversubscribe-able. The method also includes performing at least one of: declaring an amount of the second capacity un-useable to reduce oversubscription of the caching resources; allocating system memory address space of the multi-level system memory so that requests associated with lower priority users will not compete with requests associated with the higher priority users for the caching resources.
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