公开(公告)号：US20210035886A1

公开(公告)日：2021-02-04

申请号：US16529639

申请日：2019-08-01

申请人： Intel Corporation

发明人： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065

摘要： A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

公开(公告)号：US11004768B2

公开(公告)日：2021-05-11

申请号：US16529639

申请日：2019-08-01

申请人： Intel Corporation

发明人： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40

摘要： A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.