公开(公告)号：US20210035886A1

公开(公告)日：2021-02-04

申请号：US16529639

申请日：2019-08-01

申请人： Intel Corporation

发明人： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065

摘要： A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

公开(公告)号：US20190304805A1

公开(公告)日：2019-10-03

申请号：US15941809

申请日：2018-03-30

申请人： Intel Corporation

发明人： Jiongxin Lu ,  Aravindha Antoniswamy ,  Jinlin Wang ,  Ashutosh Srivastava

IPC分类号： H01L21/48 ,  H01L23/498

摘要： An electronic package including a substrate. The substrate includes a first solder material that is applied adjacent a periphery of the substrate. The substrate also includes a second solder material having properties different than the first solder material that is applied adjacent a periphery of a keep in zone of the substrate.

公开(公告)号：US11869824B2

公开(公告)日：2024-01-09

申请号：US16672858

申请日：2019-11-04

申请人： Intel Corporation

发明人： Kyle J. Arrington ,  Aaron McCann ,  Kelly Lofgreen ,  Elah Bozorg-Grayeli ,  Aravindha Antoniswamy ,  Joseph B. Petrini

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L23/3735 ,  H01L23/3733 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32506 ,  H01L2224/73253

摘要： A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.

公开(公告)号：US11004768B2

公开(公告)日：2021-05-11

申请号：US16529639

申请日：2019-08-01

申请人： Intel Corporation

发明人： Muhammad S. Islam ,  Enisa Harris ,  Suzana Prstic ,  Sergio Chan Arguedas ,  Sachin Deshmukh ,  Aravindha Antoniswamy ,  Elah Bozorg-Grayeli

IPC分类号： H01L23/42 ,  H01L23/367 ,  H01L23/10 ,  H05K7/20 ,  H01L23/00 ,  H01L25/065 ,  H01L23/40

摘要： A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.

公开(公告)号：US20240222288A1

公开(公告)日：2024-07-04

申请号：US18090140

申请日：2022-12-28

申请人： Intel Corporation

发明人： David Shia ,  Timothy Gosselin ,  Aravindha Antoniswamy ,  Sergio Antonio Chan Arguedas ,  Elah Bozorg-Grayeli ,  Johnny Cook, JR. ,  Steven Klein ,  Rick Canham

IPC分类号： H01L23/544 ,  H01L23/00 ,  H01L23/427 ,  H01L23/49

CPC分类号： H01L23/544 ,  H01L23/427 ,  H01L23/49 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/08113 ,  H01L2224/48229 ,  H01L2924/15165 ,  H01L2924/1711 ,  H01L2924/173 ,  H01L2924/17724 ,  H01L2924/1776

摘要： Integrated circuit (IC) device substrates and structures for mating and aligning with sockets. An IC device may include a frame on and around a substrate, which may include glass or silicon. The frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. A heat spreader may be coupled to an IC die and extend beyond the substrate or be coupled to the frame. The heat spreader may include a heat pipe. The IC device may be part of an IC system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.

公开(公告)号：US11881438B2

公开(公告)日：2024-01-23

申请号：US16746732

申请日：2020-01-17

申请人： Intel Corporation

发明人： Elah Bozorg-Grayeli ,  Kyle Arrington ,  Sergio Chan Arguedas ,  Aravindha Antoniswamy

IPC分类号： H01L23/373 ,  H01L23/367 ,  H01L23/16 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/3733 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/16 ,  H01L23/367 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/3511

摘要： A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.

公开(公告)号：US20210134698A1

公开(公告)日：2021-05-06

申请号：US16672858

申请日：2019-11-04

申请人： Intel Corporation

发明人： Kyle J. Arrington ,  Aaron McCann ,  Kelly Lofgreen ,  Elah Bozorg-Grayeli ,  Aravindha Antoniswamy ,  Joseph B. Petrini

IPC分类号： H01L23/373 ,  H01L23/00 ,  H01L25/00

摘要： A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.

公开(公告)号：US11923268B2

公开(公告)日：2024-03-05

申请号：US16781475

申请日：2020-02-04

申请人： INTEL CORPORATION

发明人： Jesus Gerardo Reyes Schuldes ,  Shankar Devasenathipathy ,  Pramod Malatkar ,  Aravindha Antoniswamy ,  Kyle Arrington

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H05K1/02

CPC分类号： H01L23/3675 ,  H01L21/4814 ,  H01L23/373 ,  H01L24/16 ,  H01L24/73 ,  H05K1/0204 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/1532

摘要： Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.

公开(公告)号：US20210242105A1

公开(公告)日：2021-08-05

申请号：US16781475

申请日：2020-02-04

申请人： INTEL CORPORATION

发明人： Jesus Gerardo Reyes Schuldes ,  Shankar Devasenathipathy ,  Pramod Malatkar ,  Aravindha Antoniswamy ,  Kyle Arrington

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L21/48 ,  H01L23/00 ,  H05K1/02

摘要： Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.

公开(公告)号：US20210225729A1

公开(公告)日：2021-07-22

申请号：US16746732

申请日：2020-01-17

申请人： Intel Corporation

发明人： Elah Bozorg-Grayeli ,  Kyle Arrington ,  Sergio Chan Arguedas ,  Aravindha Antoniswamy

IPC分类号： H01L23/373 ,  H01L23/16 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48

摘要： A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.