公开(公告)号：US20160182509A1

公开(公告)日：2016-06-23

申请号：US14582098

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： TOMASZ KANTECKI ,  NIALL D. MCDONNELL

IPC: H04L29/06

CPC classification number: H04L63/0442

Abstract: Various embodiments are generally directed to techniques to distribute encrypted packets among multiple cores in a load-balanced manner for further processing. An apparatus may include a processor component; a decryption component to decrypt an encrypted packet to generate a decrypted packet from the encrypted packet, the encrypted packet comprising a header that comprises at least one field of information; a hash component to generate a header hash from the at least one field of information during decryption of at least a portion of the encrypted packet by the decryption component, the header hash comprising a smaller quantity of bits than the at least one field of information; and a distribution component to select a first core of multiple cores coupled to the processor component based on the header hash and to transmit the decrypted packet to the first core from the processor component. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及以负载平衡方式在多个核之间分配加密分组以进行进一步处理的技术。 设备可以包括处理器组件; 解密组件，用于解密加密分组以从加密分组生成解密分组，所述加密分组包括包含至少一个信息字段的报头; 散列组件，用于在由所述解密组件解密所述加密分组的至少一部分期间从所述至少一个信息字段生成标题散列，所述标题散列包括比所述至少一个信息字段少的位数; 以及分发组件，用于基于所述头部散列来选择耦合到所述处理器组件的多个核心的第一核心，并且从所述处理器组件向所述第一核心传送所述解密的分组。 描述和要求保护其他实施例。

公开(公告)号：US20180191630A1

公开(公告)日：2018-07-05

申请号：US15394488

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： JONATHAN KENNY ,  NIALL D. MCDONNELL ,  ANDREW CUNNINGHAM ,  DEBRA BERNSTEIN ,  WILLIAM G. BURROUGHS ,  HUGH WILKINSON

IPC: H04L12/863 ,  H04L12/801 ,  H04L12/927

CPC classification number: H04L47/6255 ,  G06F13/00 ,  H04L47/39

Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

公开(公告)号：US20180004662A1

公开(公告)日：2018-01-04

申请号：US15201348

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： ANDREW CUNNINGHAM ,  MARK D. GRAY ,  ALEXANDER LECKEY ,  CHRIS MACNAMARA ,  STEPHEN T. PALERMO ,  PIERRE LAURENT ,  NIALL D. MCDONNELL ,  TOMASZ KANTECKI ,  PATRICK FLEMING

IPC: G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/06 ,  G06F12/0831 ,  G06F12/126 ,  G06F2212/283 ,  G06F2212/621

Abstract: An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.