公开(公告)号：US11501733B2

公开(公告)日：2022-11-15

申请号：US16542279

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Ajit Joshi ,  Ravi Ranganathan ,  Perazhi Sameer Kalathil ,  Jun Jiang ,  Geethacharan Rajagopalan ,  Nandini Mahendran ,  Gary Smith

IPC: G09G5/00 ,  G06F1/3206 ,  G06F1/3296 ,  G06F13/16 ,  G06F9/54 ,  G06F9/38 ,  G06F30/30

Abstract: The present disclosure is directed to systems and methods of transferring bulk data, such as OLED compensation mask data, generated by a source device to a sink device using a high-bandwidth embedded DisplayPort (eDP) connection contemporaneous with an ENABLED Panel Self-Refresh (PSR) mode. Upon ENABLING the PSR mode, the source control circuitry causes the source transmitter circuitry, the sink receiver circuitry, and the eDP high-bandwidth communication link to remain active rather than inactive. The source control circuitry generates one or more data transport units (DTUs) having a header portion that contains data indicative of the presence of a bulk data payload and the non-display status of the bulk data payload carried by the DTUs.

公开(公告)号：US10971085B2

公开(公告)日：2021-04-06

申请号：US16242603

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Nandini Mahendran ,  Ajit Joshi ,  Shravan Kumar Belagal Math ,  Sherine Abdelhak

IPC: G09G5/00 ,  G09G3/34 ,  G09G3/20 ,  G06F1/3234

Abstract: The present disclosure is directed to systems and methods of optimizing display image quality on display devices having a plurality of display power modes. Each power mode has associated therewith a respective baseline allowable percentage of distorted pixels and a baseline first relationship between an original pixel value and boosted pixel value. Display control circuitry determines a baseline second relationship using the baseline percentage of distorted pixels and the baseline first relationship. The display control circuitry selects a plurality of test distorted original pixel values and determines a respective test first relationship. Using the test distorted original pixel value, the respective test first relationship, and the baseline second relationship, the display control circuitry determines a respective PSNR and value indicative of the change in display image quality for each of the test distorted original pixel values.

公开(公告)号：US20220366861A1

公开(公告)日：2022-11-17

申请号：US17735548

申请日：2022-05-03

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Nandini Mahendran ,  Ajit Joshi ,  Shravan Kumar Belagal Math ,  Sherine Abdelhak

IPC: G09G3/34 ,  G09G3/20 ,  G06F1/3234

Abstract: The present disclosure is directed to systems and methods of optimizing display image quality on display devices having a plurality of display power modes. An example apparatus includes processor circuitry to execute instructions to: determine a baseline allowable percentage of distorted pixels for a power mode of a display; determine a baseline first relationship between an original pixel value and a boosted pixel value for the power mode; determine a baseline second relationship based on the baseline allowable percentage and the baseline first relationship; select a plurality of test distorted pixel percentages; determine, for respective selected test distorted pixel percentages, a corresponding test relationship between an original pixel color value distribution and a boosted pixel color value distribution based on the baseline second relationship; determine, for respective test relationships, a respective test peak signal to noise ratio (PSNR); determine, for the respective test PSNRs, respective values indicative of the change in image quality for the test distorted pixel percentages; and select, as the operating distorted original pixel percentage value, one of the test distorted pixel percentages based on the values.

公开(公告)号：US11289006B2

公开(公告)日：2022-03-29

申请号：US17188807

申请日：2021-03-01

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Ajit Joshi ,  Jun Jiang ,  Sherine Abdelhak ,  Shravan Kumar Belagal Math ,  Nandini Mahendran

IPC: G09G3/20

Abstract: Example display power management control circuitry is to determine a baseline image quality parameter associated with a baseline display power mode based on: a baseline first relationship parameter associated with a first relationship between original and boosted pixel values; a baseline percentage of pixels having a color value; and a baseline second relationship parameter associated with a second relationship between the numbers of original pixel values and boosted pixel values; determine a value of a subsequent first relationship parameter based on an adjusted second relationship parameter and a second percentage of pixels having the color value; determine a second image quality parameter associated with the subsequent first relationship parameter, the adjusted second relationship parameter, and the second percentage of pixels; and select the subsequent first relationship parameter and the adjusted second relationship parameter based on comparing the second image quality parameter to the baseline image quality parameter.

公开(公告)号：US20210183322A1

公开(公告)日：2021-06-17

申请号：US17186377

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Nandini Mahendran ,  Ajit Joshi ,  Shravan Kumar Belagal Math ,  Sherine Abdelhak

IPC: G09G3/34 ,  G09G3/20 ,  G06F1/3234

Abstract: The present disclosure is directed to systems and methods of optimizing display image quality on display devices having a plurality of display power modes. An example apparatus includes processor circuitry to execute instructions to: determine a baseline allowable percentage of distorted pixels for a power mode of a display; determine a baseline first relationship between an original pixel value and a boosted pixel value for the power mode; determine a baseline second relationship based on the baseline allowable percentage and the baseline first relationship; select a plurality of test distorted pixel percentages; determine, for respective selected test distorted pixel percentages, a corresponding test relationship between an original pixel color value distribution and a boosted pixel color value distribution based on the baseline second relationship; determine, for respective test relationships, a respective test peak signal to noise ratio (PSNR); determine, for the respective test PSNRs, respective values indicative of the change in image quality for the test distorted pixel percentages; and select, as the operating distorted original pixel percentage value, one of the test distorted pixel percentages based on the values.

公开(公告)号：US10937358B2

公开(公告)日：2021-03-02

申请号：US16456125

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Ajit Joshi ,  Jun Jiang ,  Sherine Abdelhak ,  Shravan Kumar Belagal Math ,  Nandini Mahendran

IPC: G09G3/20

Abstract: The present disclosure is directed to systems and methods of reducing display image power consumption while maintaining image quality on display devices having a plurality of display power modes. Each display power mode has associated therewith a defined baseline value (K1,BASELINE) first relationship. A display image includes a baseline percentage under-boosted pixels (Xi,BASELINE). Using the first relationship value (K1,BASELINE) and the pixel percentage (Xi,BASELINE), a baseline second relationship value is determined (K0,BASELINE). The value associated with the second relationship is adjusted to a first plurality of values. At each value, the value associated with the pixel percentage is adjusted to each of a second plurality of values. At each combination of second relationship value and pixel percentage, a respective first relationship value is determined. A first relationship value, second relationship value are selected to provide a reduced power consumption while maintaining image quality.

公开(公告)号：US11663986B2

公开(公告)日：2023-05-30

申请号：US17735548

申请日：2022-05-03

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Nandini Mahendran ,  Ajit Joshi ,  Shravan Kumar Belagal Math ,  Sherine Abdelhak

IPC: G09G5/00 ,  G09G3/34 ,  G09G3/20 ,  G06F1/3234

CPC classification number: G09G3/3406 ,  G06F1/3265 ,  G09G3/2003 ,  G09G2320/02 ,  G09G2320/0271 ,  G09G2330/021 ,  Y02D10/00

Abstract: The present disclosure is directed to systems and methods of optimizing display image quality on display devices having a plurality of display power modes. An example apparatus includes processor circuitry to execute instructions to: determine a baseline allowable percentage of distorted pixels for a power mode of a display; determine a baseline first relationship between an original pixel value and a boosted pixel value for the power mode; determine a baseline second relationship based on the baseline allowable percentage and the baseline first relationship; select a plurality of test distorted pixel percentages; determine, for respective selected test distorted pixel percentages, a corresponding test relationship between an original pixel color value distribution and a boosted pixel color value distribution based on the baseline second relationship; determine, for respective test relationships, a respective test peak signal to noise ratio (PSNR); determine, for the respective test PSNRs, respective values indicative of the change in image quality for the test distorted pixel percentages; and select, as the operating distorted original pixel percentage value, one of the test distorted pixel percentages based on the values.

公开(公告)号：US11348538B2

公开(公告)日：2022-05-31

申请号：US17186377

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Nandini Mahendran ,  Ajit Joshi ,  Shravan Kumar Belagal Math ,  Sherine Abdelhak

IPC: G09G5/00 ,  G09G3/34 ,  G09G3/20 ,  G06F1/3234

Abstract: The present disclosure is directed to systems and methods of optimizing display image quality on display devices having a plurality of display power modes. An example apparatus includes processor circuitry to execute instructions to: determine a baseline allowable percentage of distorted pixels for a power mode of a display; determine a baseline first relationship between an original pixel value and a boosted pixel value for the power mode; determine a baseline second relationship based on the baseline allowable percentage and the baseline first relationship; select a plurality of test distorted pixel percentages; determine, for respective selected test distorted pixel percentages, a corresponding test relationship between an original pixel color value distribution and a boosted pixel color value distribution based on the baseline second relationship; determine, for respective test relationships, a respective test peak signal to noise ratio (PSNR); determine, for the respective test PSNRs, respective values indicative of the change in image quality for the test distorted pixel percentages; and select, as the operating distorted original pixel percentage value, one of the test distorted pixel percentages based on the values.

公开(公告)号：US20210183300A1

公开(公告)日：2021-06-17

申请号：US17188807

申请日：2021-03-01

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Ajit Joshi ,  Jun Jiang ,  Sherine Abdelhak ,  Shravan Kumar Belagal Math ,  Nandini Mahendran

IPC: G09G3/20

Abstract: Example display power management control circuitry is to determine a baseline image quality parameter associated with a baseline display power mode based on: a baseline first relationship parameter associated with a first relationship between original and boosted pixel values; a baseline percentage of pixels having a color value; and a baseline second relationship parameter associated with a second relationship between the numbers of original pixel values and boosted pixel values; determine a value of a subsequent first relationship parameter based on an adjusted second relationship parameter and a second percentage of pixels having the color value; determine a second image quality parameter associated with the subsequent first relationship parameter, the adjusted second relationship parameter, and the second percentage of pixels; and select the subsequent first relationship parameter and the adjusted second relationship parameter based on comparing the second image quality parameter to the baseline image quality parameter.

公开(公告)号：US20200043440A1

公开(公告)日：2020-02-06

申请号：US16542279

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Junhai Qiu ,  Ajit Joshi ,  Ravi Ranganathan ,  Perazhi Sameer Kalathil ,  Jun Jiang ,  Geethacharan Rajagopalan ,  Nandini Mahendran ,  Gary Smith

IPC: G09G5/00 ,  G06F1/3206 ,  G06F1/3296 ,  G06F17/50 ,  G06F9/54 ,  G06F9/38 ,  G06F13/16

Abstract: The present disclosure is directed to systems and methods of transferring bulk data, such as OLED compensation mask data, generated by a source device to a sink device using a high-bandwidth embedded DisplayPort (eDP) connection contemporaneous with an ENABLED Panel Self-Refresh (PSR) mode. Upon ENABLING the PSR mode, the source control circuitry causes the source transmitter circuitry, the sink receiver circuitry, and the eDP high-bandwidth communication link to remain active rather than inactive. The source control circuitry generates one or more data transport units (DTUs) having a header portion that contains data indicative of the presence of a bulk data payload and the non-display status of the bulk data payload carried by the DTUs.