公开(公告)号：US20210224155A1

公开(公告)日：2021-07-22

申请号：US17225777

申请日：2021-04-08

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Narasimha LANKA

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30

Abstract: A memory device having on-die error checking and correction (ECC) circuitry can provide uncorrected data in response to a read command. The ECC circuitry can perform error correction for errors detected, generating the corrected data in parallel with providing the uncorrected data. The memory device stores the corrected data internally to the memory device. When an error is detected, the memory device provides an indication to the memory controller, which can then request the corrected data.

公开(公告)号：US20220011795A1

公开(公告)日：2022-01-13

申请号：US17448902

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Michael RIFANI ,  Gregory IOVINO ,  Roman RECHTER ,  Grant MCFARLAND ,  Nasser A. KURD ,  Eric FETZER ,  Kurt HENINGER ,  Qinxin YU ,  Preethi RAMASWAMY ,  Monib AHMED ,  Pauline GOITIA ,  Narasimha LANKA ,  Mohammad RASHID ,  Kit Seong WONG

IPC: G05F1/46 ,  G01R31/26 ,  G05B13/02

Abstract: Examples relate to control apparatus, a control device, a method and a computer program for determining a device-specific supply voltage for a semiconductor device, and to a corresponding semiconductor device and corresponding systems. The control apparatus is configured to obtain measurement data of measurement circuitry of the semiconductor device, the measurement data being related to a progress of aging of the semiconductor device. The control apparatus is configured to determine the device-specific supply voltage of the semiconductor device based on the measurement data. The control apparatus is configured to provide information on the device-specific supply voltage for a supply voltage control apparatus.

公开(公告)号：US20210225827A1

公开(公告)日：2021-07-22

申请号：US17213791

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Narasimha LANKA ,  Lohit YERVA ,  Mohammad RASHID ,  Kuljit S. BAINS

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/538

Abstract: A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.