公开(公告)号：US20210181831A1

公开(公告)日：2021-06-17

申请号：US17181832

申请日：2021-02-22

Applicant: Intel Corporation

Inventor： Praveen MOSALIKANTI ,  Nasser A. KURD ,  Alexander GENDLER

IPC: G06F1/3296 ,  H03L7/093 ,  G01R19/25 ,  H03L7/095 ,  H03K5/24 ,  H03K19/20

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

公开(公告)号：US20240085973A1

公开(公告)日：2024-03-14

申请号：US18514807

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Praveen MOSALIKANTI ,  Nasser A. KURD ,  Alexander GENDLER

IPC: G06F1/3296 ,  G01R19/25 ,  H03K5/24 ,  H03K19/20 ,  H03L7/093 ,  H03L7/095

CPC classification number: G06F1/3296 ,  G01R19/2513 ,  H03K5/24 ,  H03K19/20 ,  H03L7/093 ,  H03L7/095

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

公开(公告)号：US20160006443A1

公开(公告)日：2016-01-07

申请号：US14831694

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： Amr M. LOTFY ,  Mohamed A. ABDELSALAM ,  Mohammed W. EL MAHALAWY ,  Nasser A. KURD ,  Mohamed A. ABDELMONEUM

IPC: H03L7/099 ,  H03L7/087

CPC classification number: H03L7/00 ,  H03K3/0315 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/0992

Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.

公开(公告)号：US20220150006A1

公开(公告)日：2022-05-12

申请号：US17093679

申请日：2020-11-10

Applicant: Intel Corporation

Inventor： Michael SHUSTERMAN ,  John FALLIN ,  Ana M. YEPES ,  Dong-Ho HAN ,  Nasser A. KURD ,  Tomer LEVY ,  Ehud RESHEF ,  Arik GIHON ,  Ido OUZIELI ,  Yevgeni SABIN ,  Maor TAL ,  Zhongsheng WANG ,  Amit ZEEVI

IPC: H04L5/00 ,  H04W72/04

Abstract: A wireless communication device for communicating across a wireless communication channel includes one or more processors configured to determine whether a further device is generating a radio frequency interference at an operating frequency; transmit a request message to the further device requesting the further device vacate the operating frequency based on the determination that the further device is generating radio frequency interference; receive a response message from the further device; and generate an instruction based on the response message.

公开(公告)号：US20220011795A1

公开(公告)日：2022-01-13

申请号：US17448902

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Michael RIFANI ,  Gregory IOVINO ,  Roman RECHTER ,  Grant MCFARLAND ,  Nasser A. KURD ,  Eric FETZER ,  Kurt HENINGER ,  Qinxin YU ,  Preethi RAMASWAMY ,  Monib AHMED ,  Pauline GOITIA ,  Narasimha LANKA ,  Mohammad RASHID ,  Kit Seong WONG

IPC: G05F1/46 ,  G01R31/26 ,  G05B13/02

Abstract: Examples relate to control apparatus, a control device, a method and a computer program for determining a device-specific supply voltage for a semiconductor device, and to a corresponding semiconductor device and corresponding systems. The control apparatus is configured to obtain measurement data of measurement circuitry of the semiconductor device, the measurement data being related to a progress of aging of the semiconductor device. The control apparatus is configured to determine the device-specific supply voltage of the semiconductor device based on the measurement data. The control apparatus is configured to provide information on the device-specific supply voltage for a supply voltage control apparatus.

公开(公告)号：US20160204787A1

公开(公告)日：2016-07-14

申请号：US14127963

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Amr M. LOTFY ,  Mohamed A. ABDELSALAM ,  Mamdouh O. ABD EL-MEJEED ,  Nasser A. KURD ,  Mohamed A. ABDELMONEUM ,  Mark ELZINGA ,  Young Min PARK ,  Jagannadha R. RAPETA ,  Surya MUSUNURI

IPC: H03L7/10 ,  G04F10/00 ,  H03L7/099

CPC classification number: H03L7/105 ,  G04F10/005 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/103 ,  H03L2207/06

Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Abstract translation: 描述了具有锁相环的集成电路（IC），具有快速锁定能力。 IC包括：提供参考时钟的节点; 数字控制振荡器（DCO），用于产生输出时钟; 耦合到DCO的分频器，分频器分频输出时钟并产生反馈时钟; 以及控制逻辑，可操作以复位DCO和分频器，并且可操作以与参考时钟同步地释放复位。 提供了一种用于归零相位误差的装置，其包括提供参考时钟的第一节点; 提供反馈时钟的第二节点; 耦合到第一和第二节点的时间 - 数字转换器，以测量参考和反馈时钟之间的相位误差; 数字环路滤波器; 以及控制单元，用于调整所测量的相位误差，并向数字环路滤波器提供经调整的相位误差。