公开(公告)号：US20220358061A1

公开(公告)日：2022-11-10

申请号：US17873035

申请日：2022-07-25

Applicant: Intel Corporation

Inventor： Jai Ram SILIVERI ,  Pooja K. JADHAV ,  Sampath DAKSHINAMURTHY ,  Mohammad M. RASHID ,  Lohit YERVA

IPC: G06F13/16

Abstract: In a memory subsystem, a physical interface (PHY) has an unmatched architecture. To compensate for the unmatched architecture, the PHY has variable delay compensation to adjust for propagation mismatch of analog signals in the data (DQ) path and data strobe (DQS) path of the PHY. The variable delay compensation can be provided by adjusting the operation of a digital component of the PHY to introduce the delay compensation.

公开(公告)号：US20210225827A1

公开(公告)日：2021-07-22

申请号：US17213791

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Narasimha LANKA ,  Lohit YERVA ,  Mohammad RASHID ,  Kuljit S. BAINS

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/538

Abstract: A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.