公开(公告)号：US20190386665A1

公开(公告)日：2019-12-19

申请号：US16455247

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Oren Shalita ,  Roy Sofer ,  Alon Cohen ,  Sharon Heruti ,  Natarajan Karthik ,  Kailash Chandrashekar

IPC: H03L7/085 ,  H03L7/081 ,  G01S7/03 ,  G04F10/00

Abstract: An EC platform including a controller to control multiple integrated circuits (ICs) to synchronize an operational internal clock signal of an IC with a master clock signal. The controller generates commands for the IC to measure a phase difference or latency difference between an initial internal clock signal of the IC and an input clock signal to the IC from a parent IC. The controller further receives a difference signal from the IC to indicate the phase or latency difference. The IC includes a measurement circuit to measure the phase or latency difference, and to generate a difference signal to indicate the phase or latency difference. The IC further includes a synchronization clock generator to generate, based on the initial internal clock signal and the difference signal, an operational internal clock signal synchronized with the master clock signal. Other embodiments may also be described and claimed.

公开(公告)号：US11171655B2

公开(公告)日：2021-11-09

申请号：US16455247

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Oren Shalita ,  Roy Sofer ,  Alon Cohen ,  Sharon Heruti ,  Natarajan Karthik ,  Kailash Chandrashekar

IPC: H03L7/085 ,  G04F10/00 ,  G01S7/03 ,  H03L7/081

Abstract: An EC platform including a controller to control multiple integrated circuits (ICs) to synchronize an operational internal clock signal of an IC with a master clock signal. The controller generates commands for the IC to measure a phase difference or latency difference between an initial internal clock signal of the IC and an input clock signal to the IC from a parent IC. The controller further receives a difference signal from the IC to indicate the phase or latency difference. The IC includes a measurement circuit to measure the phase or latency difference, and to generate a difference signal to indicate the phase or latency difference. The IC further includes a synchronization clock generator to generate, based on the initial internal clock signal and the difference signal, an operational internal clock signal synchronized with the master clock signal. Other embodiments may also be described and claimed.