公开(公告)号：US09891691B2

公开(公告)日：2018-02-13

申请号：US14039220

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Naveen Gopal Reddy ,  Bharath Kumar ,  Robert E. Gough

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3243 ,  Y02D10/152

Abstract: Methods and apparatus relating to reducing pin count requirements for implementation of interconnect idle state(s) are described. In one embodiment, logic receives a general purpose input signal on a signal pin of an Input/Output (I/O) complex logic in response to a control signal. An I/O device (e.g., coupled to the I/O complex logic) enters a low power consumption state in response to the control signal. The logic receives a wake signal on the signal pin of the I/O complex logic and the I/O device exits the low power consumption state in response to the wake signal. Other embodiments are also claimed and disclosed.