公开(公告)号：US12124856B2

公开(公告)日：2024-10-22

申请号：US17211549

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Aamir Bohra ,  Vincent Zimmer ,  Robert E. Gough ,  Xiang Ma ,  Jabeena Begum Gaibusab

IPC: G06F9/4401 ,  G06F8/65 ,  G06F15/78 ,  G06F21/57

CPC classification number: G06F9/4411 ,  G06F15/7807 ,  G06F8/65 ,  G06F9/4401 ,  G06F21/572

Abstract: During a computing system boot sequence, reference firmware provided by a computing system component supplies Advanced Configuration and Power Interface (ACPI) code that generates ACPI tables and definition blocks to a bootloader. During a boot sequence, the reference firmware receives an indication from the bootloader which components the reference firmware is to initialize. As part of component initialization performed by the reference firmware, the reference firmware populates hand-off data structures (e.g., hand-off blocks (HOBs)) with ACPI code (AML code) that, when executed by the bootloader, generates and populates ACPI tables (e.g., DSDT and SSDT tables) and definition blocks with information pertinent to the initialization and runtime management of computing system components. Component initialization and runtime configuration workarounds can be implemented in the bootloader incorporating reference firmware updates provided by the component vendor.

公开(公告)号：US09961478B2

公开(公告)日：2018-05-01

申请号：US14450482

申请日：2014-08-04

Applicant: Intel Corporation

Inventor： David W. Browning ,  Kristoffer D. Fleming ,  Robert E. Gough ,  Guy G. Sotomayor ,  Vasudev Bibikar ,  Ankush Varma

IPC: H04W4/00 ,  H04W84/20

CPC classification number: H04W4/70 ,  H04W84/20

Abstract: The present disclosure is directed to logging random “chirps” of IoT devices and rebroadcasting these chirps to other devices on demand. An apparatus consistent with the present disclosure includes a transmitter to communicate with a network of wireless-communication-enabled devices. The apparatus also includes a receiver to detect communications transmitted from the wireless-communication-enabled device. Further, the apparatus includes control unit logic to tally the number of electrical signals emitted from each wireless-communication-enabled device. In addition, the apparatus includes memory to store the number of emitted electrical signals. The apparatus further includes a power unit electrically coupled to the transmitter, receiver, and memory.

公开(公告)号：US09841997B2

公开(公告)日：2017-12-12

申请号：US14750212

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Kristoffer D. Fleming ,  Eugene Gorbatov ,  Robert E. Gough ,  Krishnakanth V. Sistla

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F9/4893 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/455

Abstract: An apparatus and method for performing high performance instruction emulation. One embodiment of the invention includes a processor to process an instruction set including high-power and standard instructions comprising: an analysis module to determine whether a number of high-power instructions within a specified window are above or below a specified threshold; an execution mode selection module to select a native execution of the high-power instructions if the number of high-power instructions are above the specified threshold or to select an emulated execution of the high-power instructions if the number of high-power instructions are below the specified threshold.

公开(公告)号：US09552316B2

公开(公告)日：2017-01-24

申请号：US14229870

申请日：2014-03-29

Applicant: INTEL CORPORATION

Inventor： Nathaniel L. Desimone ,  Robert E. Gough ,  Sean C. Dardis

IPC: G06F13/38 ,  G06F9/44 ,  G06F13/42

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/382 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to execute a basic input/output system (BIOS), determine a respective impedance state for each of one or more pins in an M.2 physical interface, determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device. Other embodiments are described and claimed.

Abstract translation: 描述了自适应接口支持的技术。 在一个实施例中，例如，设备可以包括其硬件中的至少一部分的逻辑，用于执行基本输入/输出系统（BIOS）的逻辑，为每个的一个或多个引脚确定相应的阻抗状态 M.2物理接口，基于一个或多个引脚的阻抗状态确定与M.2物理接口耦合的外围设备的接口类型，并且在BIOS的执行期间控制外围设备的操作状态， 基于外围设备的接口类型。 描述和要求保护其他实施例。

公开(公告)号：US20160209912A1

公开(公告)日：2016-07-21

申请号：US14757924

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Robert E. Gough

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/325 ,  G06F9/4418 ,  G06F13/42 ,  H04L49/15 ,  Y02D10/151 ,  Y02D50/20

Abstract: A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.

Abstract translation: 一种串行点对点链路接口，用于实现处理器和设备之间的通信，高速串行点对点链路接口包括传输串行数据的发送器，接收器反序列化串行数据，以及控制逻辑来实现 一个协议栈。 协议栈支持多个功率管理状态，包括其中维持供电电压的有效状态，第一关闭状态和不向设备提供电源电压的第二关闭状态。 协议栈提供默认恢复时间，以允许设备在访问设备之前开始从第一个关闭状态到活动状态的转换。 协议栈进一步提供在默认恢复时间到期之前访问设备，以完成基于设备通告的恢复时间的转换。

公开(公告)号：US20160109925A1

公开(公告)日：2016-04-21

申请号：US14978340

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Paul S. Diefenbaugh ,  Robert E. Gough ,  Yuval Bachrach ,  Mikal C. Hunsaker ,  Rafi Ben-Tal ,  Ilan Pardo ,  Gideon Prat ,  David J. Harriman

IPC: G06F1/32

CPC classification number: G06F1/325 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3278 ,  G06F1/3287 ,  Y02D10/157 ,  Y02D10/171

Abstract: A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.

Abstract translation: 提供了一种芯片系统（SoC），包括处理核心和根系统。 事务请求在根组合的根端口和设备之间传送，根端口包括电空闲（EI）出口检测电路和参考时钟源。 根端口支持第一链路状态，其中根端口的参考时钟源和EI出口检测电路被禁用，但保持共模电压，第二链路状态，其中参考时钟源和EI退出检测 电路被禁用，并且不保持共模电压。 根据服务等待时间要求小于阈值，根据服务等待时间要求大于或等于阈值，根端口转换到第一链路状态。

公开(公告)号：US10139889B2

公开(公告)日：2018-11-27

申请号：US14998158

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Robert E. Gough

IPC: G06F1/32 ,  G06F13/42 ,  G06F9/44 ,  H04L12/933 ,  G06F9/4401

Abstract: A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.

公开(公告)号：US09965293B2

公开(公告)日：2018-05-08

申请号：US15394922

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Nathaniel L. Desimone ,  Robert E. Gough ,  Sean C. Dardis

IPC: G06F9/44 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/382 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to execute a basic input/output system (BIOS), determine a respective impedance state for each of one or more pins in an M.2 physical interface, determine an interface type for a peripheral device coupled with the M.2 physical interface based on the impedance states for the one or more pins, and control an operational state of the peripheral device during execution of the BIOS, based on the interface type for the peripheral device. Other embodiments are described and claimed.

公开(公告)号：US09696785B2

公开(公告)日：2017-07-04

申请号：US14142791

申请日：2013-12-28

Applicant: INTEL CORPORATION

Inventor： Robert E. Gough ,  Mazen G. Gedeon ,  Barnes Cooper ,  Basavaraj B. Astekar ,  Sean C. Dardis

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3231 ,  G06F1/3253 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/173 ,  Y02D50/20

Abstract: An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.

公开(公告)号：US20160209911A1

公开(公告)日：2016-07-21

申请号：US14998158

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Robert E. Gough

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/325 ,  G06F9/4418 ,  G06F13/42 ,  H04L49/15 ,  Y02D10/151 ,  Y02D50/20

Abstract: A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.

Abstract translation: 芯片上的系统（SoC）具有多核处理器，二级（L2）高速缓存控制器，二级高速缓存，集成存储器控制器和串行点到点链路接口，以实现多核之间的通信 处理器和设备。 该接口实现协议栈，并且包括发送器，用于向设备发送串行数据，接收器反序列化输入串行流。 协议栈支持多个功率管理状态，包括其中向设备提供电源电压的有效状态，第一关闭状态和不提供电源电压的第二关闭状态 到设备。 响应于设备准备进入活动状态的指示，协议栈提供在默认恢复时间到期之前访问设备以完成转换。