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    Method and apparatus for implementing a dynamic out-of-order processor pipeline
    1.
    发明授权
    Method and apparatus for implementing a dynamic out-of-order processor pipeline 有权

    公开(公告)号：US09612840B2

    公开(公告)日：2017-04-04

    申请号：US14228690

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Denis M. Khartikov ,  Naveen Neelakantam ,  John H. Kelm ,  Polychronis Xekalakis

    IPC: G06F15/76 ,  G06F15/00 ,  G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3802 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3891 ,  G06F9/46

    Abstract: A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

    INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION
    2.
    发明申请
    INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION 审中-公开
    大容量存储器重新引导的指令和逻辑

    公开(公告)号：US20160092222A1

    公开(公告)日：2016-03-31

    申请号：US14496113

    申请日：2014-09-25

    Applicant: Intel Corporation

    Inventor： David Pardo Keppel ,  Denis M. Khartikov ,  Fernando LaTorre ,  Marc Lupon ,  Grigorios Magklis ,  Naveen Neelakantam ,  Georgios Tournavitis ,  Polychronis Xekalakis

    IPC: G06F9/30

    CPC classification number: G06F9/30185 ,  G06F9/384 ,  G06F9/3857

    Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.

    Abstract translation: 处理器包括前端，解码器，分配器和退休单元。 解码器包括用于识别终点范围（EOLR）指示符的逻辑。 EOLR指示符指定体系结构寄存器和不使用体系结构寄存器的代码中的位置。 分配器包括基于EOLR指示器扫描架构寄存器到物理寄存器的映射的逻辑。 分配器还包括生成用于将体系结构寄存器与物理寄存器取消关联的请求的逻辑。 退休单位包括将架构寄存器与物理寄存器取消关联的逻辑。

    Method and apparatus to implement lazy flush in a virtually tagged cache memory
    6.
    发明授权
    Method and apparatus to implement lazy flush in a virtually tagged cache memory 有权
    在虚拟标记的高速缓冲存储器中实现延迟刷新的方法和装置

    公开(公告)号：US09009413B2

    公开(公告)日：2015-04-14

    申请号：US13724848

    申请日：2012-12-21

    Applicant: Intel Corporation

    Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Niranjan L. Cooray ,  Pedro Lopez ,  Naveen Neelakantam ,  Li-Gao Zei ,  Rami May ,  Jaroslaw Topp ,  Thomas Gaertner

    IPC: G06F12/08 ,  G11C7/10 ,  G06F12/10

    CPC classification number: G11C7/1072 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1036

    Abstract: A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.

    Abstract translation: 处理器包括处理器核心，其包括执行指令的执行单元和高速缓冲存储器。 高速缓冲存储器包括控制器，以响应于惰性冲洗指令来更新多个陈旧指示器中的每一个。 每个陈旧的指示符与相应的数据相关联，每个更新的陈旧指示符指示相应的数据是否过时。 高速缓冲存储器还包括多条高速缓存行。 每个高速缓存行将存储对应的数据和前景标签，其包括与对应的数据相关联的相应的虚拟地址，并且其包括相关联的陈旧指示符。 其他实施例被描述为所要求保护的。

    Handling of binary translated self modifying code and cross modifying code
    7.
    发明授权
    Handling of binary translated self modifying code and cross modifying code 有权
    处理二进制翻译自修改代码和交叉修改代码

    公开(公告)号：US09116729B2

    公开(公告)日：2015-08-25

    申请号：US13997694

    申请日：2012-12-27

    Applicant: Intel Corporation

    Inventor： Nirajan L. Cooray ,  David Keppel ,  Naveen Kumar ,  Ori Lempel ,  Michael Neilly ,  Naveen Neelakantam ,  H. Peter Anvin ,  Sebastian Winkel

    IPC: G06F9/455 ,  G06F12/10

    CPC classification number: G06F9/45525

    Abstract: A processor includes a processor core to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.

    Abstract translation: 处理器包括处理器核，用于执行从存储在存储器的第一页中的第一指令转换的第一翻译指令。 处理器还包括翻译指示剂代理（XTBA），用于存储从存储器中的物理图（PhysMap）读取的第一翻译指示符。 在一个实施例中，第一翻译指示符是指示在第一指令被翻译之后第一页是否已被修改。 其他实施例被描述为所要求保护的。

    Method and apparatus for implementing a dynamic out-of-order processor pipeline
    8.
    发明授权
    Method and apparatus for implementing a dynamic out-of-order processor pipeline 有权

    公开(公告)号：US10338927B2

    公开(公告)日：2019-07-02

    申请号：US15477374

    申请日：2017-04-03

    Applicant: Intel Corporation

    Inventor： Denis M. Khartikov ,  Naveen Neelakantam ,  John H. Kelm ,  Polychronis Xekalakis

    IPC: G06F15/76 ,  G06F15/00 ,  G06F9/38 ,  G06F9/30 ,  G06F9/46

    Abstract: A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

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