公开(公告)号：US20170242705A1

公开(公告)日：2017-08-24

申请号：US15589445

申请日：2017-05-08

申请人： Intel Corporation

发明人： John H. Kelm ,  David P. Keppel ,  David N. Mackintosh

IPC分类号： G06F9/30 ,  G06F12/0875

CPC分类号： G06F9/30174 ,  G06F9/4552 ,  G06F12/0875 ,  G06F2212/452

摘要： A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.

公开(公告)号：US09612840B2

公开(公告)日：2017-04-04

申请号：US14228690

申请日：2014-03-28

申请人： Intel Corporation

发明人： Denis M. Khartikov ,  Naveen Neelakantam ,  John H. Kelm ,  Polychronis Xekalakis

IPC分类号： G06F15/76 ,  G06F15/00 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3891 ,  G06F9/46

摘要： A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

公开(公告)号：US09971599B2

公开(公告)日：2018-05-15

申请号：US15589445

申请日：2017-05-08

申请人： Intel Corporation

发明人： John H. Kelm ,  David P. Keppel ,  David N. Mackintosh

IPC分类号： G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F12/0875

CPC分类号： G06F9/30174 ,  G06F9/4552 ,  G06F12/0875 ,  G06F2212/452

摘要： A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.

公开(公告)号：US10338927B2

公开(公告)日：2019-07-02

申请号：US15477374

申请日：2017-04-03

申请人： Intel Corporation

发明人： Denis M. Khartikov ,  Naveen Neelakantam ,  John H. Kelm ,  Polychronis Xekalakis

IPC分类号： G06F15/76 ,  G06F15/00 ,  G06F9/38 ,  G06F9/30 ,  G06F9/46

摘要： A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

公开(公告)号：US09870209B2

公开(公告)日：2018-01-16

申请号：US14228697

申请日：2014-03-28

申请人： Intel Corporation

发明人： John H. Kelm ,  Demos Pavlou ,  Mirem Hyuseinova

IPC分类号： G06F9/45 ,  G06F9/38 ,  G06F12/08 ,  G06F12/12 ,  G06F12/0804 ,  G06F12/0811

CPC分类号： G06F8/52 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/621

摘要： A processor includes a resource scheduler, a dispatcher, and a memory execution unit. The memory execution unit includes logic to identify an executed, unretired store operation in a memory ordered buffer, determine that the store operation is speculative, determine whether an associated cache line in a data cache is non-speculative, and determine whether to block a write of the store operation results to the data cache based upon the determination that the store operation is speculative and a determination that the associated cache line is non-speculative.

公开(公告)号：US10409763B2

公开(公告)日：2019-09-10

申请号：US14319265

申请日：2014-06-30

申请人： Intel Corporation

发明人： Patrick P. Lai ,  Ethan Schuchman ,  David Keppel ,  Denis M. Khartikov ,  Polychronis Xekalakis ,  Joshua B. Fryman ,  Allan D. Knies ,  Naveen Neelakantam ,  Gregor Stellpflug ,  John H. Kelm ,  Mirem Hyuseinova Seidahmedova ,  Demos Pavlou ,  Jaroslaw Topp

IPC分类号： G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/455

摘要： Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.