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    VARIATION TOLERANT RECONFIGURABLE REPLICA BITLINE CIRCUITS
    2.
    发明公开
    VARIATION TOLERANT RECONFIGURABLE REPLICA BITLINE CIRCUITS 审中-公开

    公开(公告)号：US20230395140A1

    公开(公告)日：2023-12-07

    申请号：US17834073

    申请日：2022-06-07

    申请人： Intel Corporation

    发明人： Naveen Kumar ,  Gururaj Shamanna ,  Jagadeesh Chandra Salaka ,  Purna Chandra Nayak

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419

    摘要： An apparatus, system, and method for improved replica bit line (RBL) operation are provided. An memory control circuit can include an RBL including a plurality of replica bit cells (RBCs) electrically coupled in series, a timer and control logic circuit situated to receive an output of the RBL, and a first multiplexer electrically coupled between the RBL and the timer and control logic circuit, the first multiplexer configured to set a replica word line (RWL) that controls, based on a state of select lines input into the first multiplexer and input provided by the timer and control logic, which of the RBCs is active.

    Handling of binary translated self modifying code and cross modifying code
    4.
    发明授权
    Handling of binary translated self modifying code and cross modifying code 有权
    处理二进制翻译自修改代码和交叉修改代码

    公开(公告)号：US09116729B2

    公开(公告)日：2015-08-25

    申请号：US13997694

    申请日：2012-12-27

    申请人： Intel Corporation

    发明人： Nirajan L. Cooray ,  David Keppel ,  Naveen Kumar ,  Ori Lempel ,  Michael Neilly ,  Naveen Neelakantam ,  H. Peter Anvin ,  Sebastian Winkel

    IPC分类号： G06F9/455 ,  G06F12/10

    CPC分类号： G06F9/45525

    摘要： A processor includes a processor core to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.

    摘要翻译： 处理器包括处理器核，用于执行从存储在存储器的第一页中的第一指令转换的第一翻译指令。 处理器还包括翻译指示剂代理（XTBA），用于存储从存储器中的物理图（PhysMap）读取的第一翻译指示符。 在一个实施例中，第一翻译指示符是指示在第一指令被翻译之后第一页是否已被修改。 其他实施例被描述为所要求保护的。

    Instruction and logic for a binary translation mechanism for control-flow security
    9.
    发明授权
    Instruction and logic for a binary translation mechanism for control-flow security 有权

    公开(公告)号：US10048965B2

    公开(公告)日：2018-08-14

    申请号：US15455886

    申请日：2017-03-10

    申请人： Intel Corporation

    发明人： Petros Maniatis ,  Shantanu Gupta ,  Naveen Kumar

    IPC分类号： G06F9/30 ,  G06F9/35 ,  G06F21/52

    摘要： A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.