公开(公告)号：US11380679B2

公开(公告)日：2022-07-05

申请号：US16141641

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez ,  Nicholas McKubre

IPC: H01L27/06 ,  H03K3/012 ,  H03J3/20 ,  H01L29/94 ,  H03H11/28 ,  H03H7/01 ,  H03H7/38 ,  H03H11/04

Abstract: Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.

公开(公告)号：US20200098746A1

公开(公告)日：2020-03-26

申请号：US16141641

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez ,  Nicholas McKubre

IPC: H01L27/06 ,  H03K3/012 ,  H03J3/20 ,  H03H11/04 ,  H03H11/28 ,  H03H7/01 ,  H03H7/38 ,  H01L29/94

Abstract: Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value. The FET capacitor structures may be operable in depletion mode and/or enhancement mode.