公开(公告)号：US20250005101A1

公开(公告)日：2025-01-02

申请号：US18217565

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Raghavan KUMAR ,  Nojan SHEYBANI ,  Vikram B. SURESH

IPC: G06F17/14

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

公开(公告)号：US20250005102A1

公开(公告)日：2025-01-02

申请号：US18599931

申请日：2024-03-08

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Raghavan KUMAR ,  Nojan SHEYBANI ,  Vikram B. SURESH

IPC: G06F17/15 ,  H04L9/00

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.