公开(公告)号：US20250005100A1

公开(公告)日：2025-01-02

申请号：US18217564

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  AppaRao CHALLAGUNDLA ,  Sanu K. MATHEW ,  Christopher B. WILKERSON ,  Adish VARTAK ,  Sachin TANEJA ,  Minxuan ZHOU ,  Lalith Dharmesh KETHARESWARAN

IPC: G06F17/14

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload.

公开(公告)号：US20170139948A1

公开(公告)日：2017-05-18

申请号：US14944828

申请日：2015-11-18

Applicant: Intel Corporation

Inventor： Himanshu KAUL ,  Mark A. ANDERS ,  Sanu K. MATHEW

IPC: G06F17/30

CPC classification number: G06F17/10 ,  G06F17/30979 ,  G06K9/00986 ,  G06K9/6276

Abstract: Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are described. In some embodiments, the KNN accelerator includes a plurality of vector partial distance computation circuits each to calculate a partial sum, a minimum sort network to sort partial sums from the plurality of vector partial distance computation circuits to find k nearest neighbor matches and a global control circuit to control aspects of operations of the plurality of vector partial distance computation circuits.

公开(公告)号：US20180293052A1

公开(公告)日：2018-10-11

申请号：US15479424

申请日：2017-04-05

Applicant: INTEL CORPORATION

Inventor： Vikram B. SURESH ,  Sanu K. MATHEW ,  Sudhir K. SATPATHY

IPC: G06F7/58 ,  H04L9/32

Abstract: An apparatus is described. The apparatus includes a plurality of physically unclonable circuits. The apparatus includes circuitry to detect which ones of the physically unclonable circuits are unstable. The apparatus also includes circuitry to couple the unstable physically unclonable circuits to a random number generator circuit.

公开(公告)号：US20180176025A1

公开(公告)日：2018-06-21

申请号：US15382362

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Vikram B. SURESH ,  Sanu K. MATHEW ,  Sudhir K. SATPATHY

IPC: H04L9/32 ,  H04L9/06

CPC classification number: H04L9/3278

Abstract: An apparatus is provided which comprises: a first stage of physically unclonable function (PUF) circuits to receive an n-bit challenge, wherein the first stage of PUF circuits comprise a subset of ‘n’ PUF cells each of which is to generate an output bit; and a first stage of cipher blocks to receive the output bits from the subset of ‘n’ PUF cells, wherein the first stage of cipher blocks is to generate a plurality of bits.

公开(公告)号：US20250005101A1

公开(公告)日：2025-01-02

申请号：US18217565

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Raghavan KUMAR ,  Nojan SHEYBANI ,  Vikram B. SURESH

IPC: G06F17/14

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

公开(公告)号：US20200036389A1

公开(公告)日：2020-01-30

申请号：US16592465

申请日：2019-10-03

Applicant: Intel Corporation

Inventor： Vikram B. SURESH ,  Sudhir K. SATPATHY ,  Sanu K. MATHEW

IPC: H03M7/30 ,  H03M7/42

Abstract: Examples herein relate to decoding tokens using speculative decoding operations to decode tokens at an offset from a token decoded by a sequential decoding operation. At a checkpoint, a determination is made as to whether tokens to be decoded by the sequential and speculative decoding operations align. If there is alignment, the speculatively decoded tokens after a discard window are committed and made available for access. If there is not alignment, the speculatively decoded tokens are discarded. A miss in alignment and a fullness level of a buffer that stores speculatively decoded tokens are assessed to determine a next offset level for a start of speculative decoding. A size of a discard window can be set using a relationship based on the offset level to improve buffer utilization and to attempt to improve changes of alignments.

公开(公告)号：US20250112772A1

公开(公告)日：2025-04-03

申请号：US18375421

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Christopher B. WILKERSON ,  Raghavan KUMAR ,  Anupam GOLDER

IPC: H04L9/30 ,  H04L9/00 ,  H04L9/08

Abstract: Bandwidth of High Bandwidth Memory (HBM) and scratch pad memory used by an Fully Homomorphic Encryption (FHE) accelerator in a System-on-Chip (SoC) during FHE relinearization is reduced by including a key generator module in the SoC. The key generator module to generate FHE public keys from a seed that is input to the SoC. The seed used by the on-die key generator module to generate FHE relinearization public keys locally within the scratch pad memory units in the SoC.

公开(公告)号：US20250112757A1

公开(公告)日：2025-04-03

申请号：US18374179

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Sanu K. MATHEW ,  Adish VARTAK ,  Christopher B. WILKERSON

IPC: H04L9/00 ,  H04L9/06

Abstract: Examples include techniques for mixed word size multiplication to facilitate operations for relinearization associated with executing a fully homomorphic encryption (FHE) workload. Examples include use of precomputed base conversion factors and decomposing large words or digits to a data size that is equal to or smaller than a machine word size associated with a multiplier datapath to facilitate the operations for relinearization.

公开(公告)号：US20250007688A1

公开(公告)日：2025-01-02

申请号：US18217561

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Sanu K. MATHEW ,  Sachin TANEJA ,  Christopher B. WILKERSON ,  Minxuan ZHOU

IPC: H04L9/00 ,  G06F17/14 ,  H04L9/30

Abstract: A reconfigurable compute circuitry to perform Fully Homomorphic Encryption (FHE) enables a full utilization of compute resources and data movement resources by mapping multiple N*1024 polynomials on to a (M*N)*1024 polynomial. To counteract the shuffling of the coefficients during Number-Theoretic-Transforms (NTT) and inverse-NTT operations, compute elements in the compute circuitry operate in a bypass mode that is enabled by a data movement instruction, to convert from the shuffled form to contiguous form without modifying the values of the coefficients.

公开(公告)号：US20250005102A1

公开(公告)日：2025-01-02

申请号：US18599931

申请日：2024-03-08

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Raghavan KUMAR ,  Nojan SHEYBANI ,  Vikram B. SURESH

IPC: G06F17/15 ,  H04L9/00

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.