公开(公告)号：US20250007687A1

公开(公告)日：2025-01-02

申请号：US18217551

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Sanu MATHEW ,  Vikram SURESH ,  Sachin TANEJA ,  Raghavan KUMAR ,  Christopher WILKERSON

IPC: H04L9/00

Abstract: Techniques for fully homomorphic encryption are described. In some examples, a register file to store polynomials is coupled to a butterfly compute path. The butterfly compute path includes a multiplier coupled to a first input and a second input to multiply the first and second input to, when enabled, generate a multiplication output, a first multiplexer coupled to an output of the multiplier and to the first input to output a selection between the output of the multiplier and the first input, an adder to add, when enabled, a third input to the selected output of the first multiplexer, a subtractor to subtract, when enabled, an output of the multiplier from the third input, and a second multiplexer coupled to an output of the multiplier and to the first input to, when enabled, output a selection between the output of the multiplier and the subtractor.

公开(公告)号：US20250005101A1

公开(公告)日：2025-01-02

申请号：US18217565

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Raghavan KUMAR ,  Nojan SHEYBANI ,  Vikram B. SURESH

IPC: G06F17/14

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.

公开(公告)号：US20250005100A1

公开(公告)日：2025-01-02

申请号：US18217564

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  AppaRao CHALLAGUNDLA ,  Sanu K. MATHEW ,  Christopher B. WILKERSON ,  Adish VARTAK ,  Sachin TANEJA ,  Minxuan ZHOU ,  Lalith Dharmesh KETHARESWARAN

IPC: G06F17/14

Abstract: Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload.

公开(公告)号：US20250007688A1

公开(公告)日：2025-01-02

申请号：US18217561

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Raghavan KUMAR ,  Sanu K. MATHEW ,  Sachin TANEJA ,  Christopher B. WILKERSON ,  Minxuan ZHOU

IPC: H04L9/00 ,  G06F17/14 ,  H04L9/30

Abstract: A reconfigurable compute circuitry to perform Fully Homomorphic Encryption (FHE) enables a full utilization of compute resources and data movement resources by mapping multiple N*1024 polynomials on to a (M*N)*1024 polynomial. To counteract the shuffling of the coefficients during Number-Theoretic-Transforms (NTT) and inverse-NTT operations, compute elements in the compute circuitry operate in a bypass mode that is enabled by a data movement instruction, to convert from the shuffled form to contiguous form without modifying the values of the coefficients.

公开(公告)号：US20250005102A1

公开(公告)日：2025-01-02

申请号：US18599931

申请日：2024-03-08

Applicant: Intel Corporation

Inventor： Sachin TANEJA ,  Sanu K. MATHEW ,  Raghavan KUMAR ,  Nojan SHEYBANI ,  Vikram B. SURESH

IPC: G06F17/15 ,  H04L9/00

Abstract: Examples include techniques for twiddle factor generation for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations by a compute element. The compute element can be included in a parallel processing device. Examples include receiving information to generate a twiddle factor for use by the compute element to execute an NTT or an iNTT computation for an N-degree polynomial, obtain data for a power of 2 of a root of unity from a memory resident on a same chip or die as the compute element and generate the twiddle factor using the obtained data based, at least in part, on the received information.