公开(公告)号：US20200285559A1

公开(公告)日：2020-09-10

申请号：US16878976

申请日：2020-05-20

Applicant: Intel Corporation

Inventor： ROLF KUEHNIS ,  PETER LACHNER

IPC: G06F11/36 ,  G06F9/455

Abstract: In one embodiment, an apparatus includes: a first hardware circuit to execute operations and a trace hardware circuit coupled to the first hardware circuit. At least one virtualization environment to be instantiated by a virtualization environment controller is to execute on the first hardware circuit. The virtualization environment controller may receive from a first virtualization environment a first trace message and a first platform description identifier to identify the first virtualization environment, remap the first platform description identifier to a second platform description identifier and send the first trace message and the second platform description identifier to the trace hardware circuit. In turn, the trace hardware circuit may send the first trace message and the second platform description identifier to a debug and test system. Other embodiments are described and claimed.

公开(公告)号：US20160170820A1

公开(公告)日：2016-06-16

申请号：US14566374

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： BEEMAN C. STRONG ,  STEPHEN J. ROBINSON ,  JASON W. BRANDT ,  PETER LACHNER

IPC: G06F11/07 ,  G06F11/34

CPC classification number: G06F11/3466 ,  G06F9/30 ,  G06F11/3636

Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.

Abstract translation: 公开了一种在调试跟踪架构中实现跟踪延迟数据分组的处理设备。 处理装置是确定与执行指令相对应的顺序相对于执行指令序列中的指令类型的其他执行指令的顺序，识别对应于第一分组类型的第一数据分组，并依次 根据订单编号对数据跟踪日志中的第一分组类型的数据分组进行排序，识别与第二分组类型对应的第二数据分组，并根据订单号对数据分组进行顺序排序 的数据跟踪日志中的第二分组类型，并将所识别的第一和第二数据分组映射到指令，其中在指令的退休之后生成第一或第二数据分组中的至少一个。