公开(公告)号：US20190096490A1

公开(公告)日：2019-03-28

申请号：US15717835

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： ALIASGAR S. MADRASWALA ,  XIN GUO ,  DAVID B. CARLTON ,  PURVAL S. SULE

IPC: G11C16/26 ,  G11C16/10

Abstract: Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.