公开(公告)号：US20180189154A1

公开(公告)日：2018-07-05

申请号：US15394261

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： FENG ZHU ,  ALIASGAR S. MADRASWALA ,  XIN GUO

IPC: G06F11/20 ,  G06F3/06 ,  G11C7/14

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G11C7/14 ,  G11C29/00 ,  G11C29/52

Abstract: Examples herein include techniques for flash page retirement following one or more defects in nonvolatile memory. In some examples, a storage controller may retire a first logical page in response to a first read error, and write data to the one or more NMV devices in a program-erase (P/E) cycle without a dummy page being programmed or generated for the retired first logical page. The storage controller may further retire a second logical page in response to a second read error, wherein the first logical page has a higher order than the second logical page in a same physical memory page.

公开(公告)号：US20190042130A1

公开(公告)日：2019-02-07

申请号：US15845596

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： NAVEEN VITTAL PRABHU ,  ALIASGAR S. MADRASWALA ,  DONIA SEBASTIAN ,  SHANKAR NATARAJAN

IPC: G06F3/06

Abstract: A system for reconfiguring flash memory from a default access operation mode (e.g., MLC, TLC, or QLC mode) to a non-default access operation mode (e.g., SLC mode) using opcode prefixes is provided. Opcode prefix logic enables the flash memory die to enter a non-default (e.g., faster) access operation mode. The non-default access operation mode is entered by providing a prefix instruction or opcode prefix to the memory controller and/or to the flash memory die prior to memory operation commands (“opcode”) for program, read, and/or erase. The flash memory die is configured to automatically exit the non-default access operation mode after a single operation, or the flash memory die is configured to exit the non-default access operation mode upon receipt of another opcode prefix.

公开(公告)号：US20190043564A1

公开(公告)日：2019-02-07

申请号：US15845500

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： ALIASGAR S. MADRASWALA ,  BHARAT M. PATHAK ,  BINH N. NGO ,  NAVEEN VITTAL PRABHU ,  KARTHIKEYAN RAMAMURTHI ,  PRANAV KALAVADE

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C8/08 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C2211/5631

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

公开(公告)号：US20190096490A1

公开(公告)日：2019-03-28

申请号：US15717835

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： ALIASGAR S. MADRASWALA ,  XIN GUO ,  DAVID B. CARLTON ,  PURVAL S. SULE

IPC: G11C16/26 ,  G11C16/10

Abstract: Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.

公开(公告)号：US20170315866A1

公开(公告)日：2017-11-02

申请号：US15443707

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： MATTHEW GOLDMAN ,  WAYNE D. TRAN ,  ALIASGAR S. MADRASWALA ,  SUNGHO PARK

IPC: G06F11/10 ,  G11C16/34 ,  G11C16/26 ,  G11C29/04 ,  G11C11/56

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/34 ,  G11C2029/0411

Abstract: An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.

公开(公告)号：US20160085668A1

公开(公告)日：2016-03-24

申请号：US14961424

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： YOGESH B. WAKCHAURE ,  ALIASGAR S. MADRASWALA ,  KRISTOPHER H. GAEWSKY ,  CHARAN SRINIVASAN

IPC: G06F12/02 ,  G11C16/10

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G11C5/147 ,  G11C11/1673 ,  G11C11/5642 ,  G11C13/0059 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C2211/5648

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

公开(公告)号：US20150380095A1

公开(公告)日：2015-12-31

申请号：US14318572

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： YOGESH B. WAKCHAURE ,  ALIASGAR S. MADRASWALA ,  KRISTOPHER H. GAEWSKY ,  CHARAN SRINIVASAN

IPC: G11C16/14 ,  G11C16/26

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G11C5/147 ,  G11C11/1673 ,  G11C11/5642 ,  G11C13/0059 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C2211/5648

Abstract: Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了提高闪存系统中部分写入的存储块的可靠性和/或性能的方法和装置。 在一些实施例中，存储设备存储对应于在非易失性存储器的部分编程的存储器块上执行的部分写入操作的信息。 至少部分地基于所存储的信息，存储器控制器逻辑然后在对非易失性存储器的读取或写入操作期间使非常易失性存储器的部分的减小的电压电平和/或偏移值应用于非易失性存储器。 还公开并要求保护其他实施例。