公开(公告)号：US11193973B2

公开(公告)日：2021-12-07

申请号：US16947084

申请日：2020-07-17

Applicant: Intel Corporation

Inventor： Rolf H. Kuehnis ,  Sankaran M. Menon ,  Patrik Eder

IPC: G01R31/3177 ,  G01R31/317

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

公开(公告)号：US11698412B2

公开(公告)日：2023-07-11

申请号：US17538482

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Rolf H. Kuehnis ,  Sankaran M. Menon ,  Patrik Eder

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31705 ,  G01R31/31715 ,  G01R31/31723

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

公开(公告)号：US11138083B2

公开(公告)日：2021-10-05

申请号：US16596154

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Patrik Eder ,  Rolf H. Kuehnis ,  Enrico D. Carrieri

IPC: G06F11/25 ,  G06F11/267 ,  G01R31/317

Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.

公开(公告)号：US09948927B2

公开(公告)日：2018-04-17

申请号：US15066762

申请日：2016-03-10

Applicant: Intel Corporation

Inventor： Rolf H. Kuehnis ,  Patrik Eder

IPC: G06F11/00 ,  H04N17/00 ,  G06K9/03 ,  G06F11/22 ,  G06K9/20 ,  G06F11/07

CPC classification number: H04N17/004 ,  G06F11/079 ,  G06F11/2294 ,  G06K9/036 ,  G06K9/2054

Abstract: Embodiments of the present disclosure provide a method and apparatus for device testing via an optical interface. In one instance, the apparatus may comprise a test controller to operate a camera to generate an image to capture test data displayed on a screen of a device under test. The test controller may be configured to extract the test data from the image, analyze the test data, and generate feedback information for the device under test, based at least in part on a result of the analysis of the test data. The camera may be included in the apparatus and communicatively coupled with the test controller. Other embodiments may be described and/or claimed.

公开(公告)号：US10481990B2

公开(公告)日：2019-11-19

申请号：US15474799

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Patrik Eder ,  Rolf H. Kuehnis ,  Enrico D. Carrieri

IPC: G06F11/267 ,  G06F11/25 ,  G01R31/317

Abstract: Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.

公开(公告)号：US20190080258A1

公开(公告)日：2019-03-14

申请号：US15703149

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Patrik Eder ,  Christian Horak ,  Joseph F. Cramer

IPC: G06N99/00 ,  G06N5/02 ,  G06N3/02

Abstract: Embodiments of the present disclosure may relate to an apparatus with an observation hub that includes a machine-learning model, where the observation hub is to determine a state of an apparatus based at least in part on the machine-learning model and trace data received from one or more trace sources, and alter an operating condition of the apparatus based at least in part on the determined state of the apparatus. Embodiments may also include a multi-buffer trace unit to change one or more of a sort rule, a trigger rule, an enforcement rule, or a filter rule of the multi-buffer trace unit based at least in part on the determined state of the apparatus. Other embodiments may be described and/or claimed.

公开(公告)号：US20220082617A1

公开(公告)日：2022-03-17

申请号：US17538482

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Rolf H. Kuehnis ,  Sankaran M. Menon ,  Patrik Eder

IPC: G01R31/3177 ,  G01R31/317

Abstract: Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

公开(公告)号：US10795399B2

公开(公告)日：2020-10-06

申请号：US15855381

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Patrik Eder ,  Rolf Kuehnis ,  Enrico Carrieri

IPC: G06F1/12 ,  G06F1/08 ,  G01R31/317 ,  G06F13/40 ,  G06F13/42 ,  G06F13/00 ,  G06F1/10 ,  H04L7/10 ,  H04J3/06 ,  H04L7/00

Abstract: One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.