公开(公告)号：US11199586B2

公开(公告)日：2021-12-14

申请号：US15837462

申请日：2017-12-11

申请人： Intel Corporation

发明人： Enrico D. Carrieri ,  John W. Kitterman ,  Keith A. Jones

IPC分类号： G01R31/3185 ,  G01R31/317

摘要： A Joint Test Access Group (JTAG) device can include a Joint Test Access Group (JTAG) port, transport layer circuitry to provide a communication to and from a debug device, and packet interpreter circuitry communicatively coupled between the JTAG port and the transport layer circuitry, the packet interpreter circuitry to translate data in a packet from the debug device into a sequence of bits to be provided to the JTAG port.

公开(公告)号：US10481990B2

公开(公告)日：2019-11-19

申请号：US15474799

申请日：2017-03-30

申请人： Intel Corporation

发明人： Patrik Eder ,  Rolf H. Kuehnis ,  Enrico D. Carrieri

IPC分类号： G06F11/267 ,  G06F11/25 ,  G01R31/317

摘要： Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a debug and test access port to debug and test the device circuit, and a switching circuit to switch a debug and test mastership between the debug and test access port and a data access port to the device circuit that is not dedicated to debug and test.

公开(公告)号：US10853289B2

公开(公告)日：2020-12-01

申请号：US16221962

申请日：2018-12-17

申请人： Intel Corporation

发明人： Amit Kumar Srivastava ,  Asad Azam ,  Rajesh Bhaskar ,  Mikal Hunsaker ,  Enrico D. Carrieri

IPC分类号： G06F13/36 ,  G06F13/364 ,  H04L12/801 ,  H04L12/835 ,  G06F13/24 ,  G06F13/16 ,  G06F13/42 ,  H04L5/16

摘要： In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.

公开(公告)号：US20190121765A1

公开(公告)日：2019-04-25

申请号：US16221962

申请日：2018-12-17

申请人： Intel Corporation

发明人： Amit Kumar Srivastava ,  Asad Azam ,  Rajesh Bhaskar ,  Mikal Hunsaker ,  Enrico D. Carrieri

IPC分类号： G06F13/364 ,  H04L12/801 ,  H04L12/835 ,  G06F13/24 ,  G06F13/16 ,  G06F13/42 ,  H04L5/16

摘要： In one embodiment, a host controller includes: a first credit tracker comprising at least one credit counter to maintain credit information for a first device; and a first credit handler to send a command code having a first predetermined value to indicate a credit request to request credit information from the first device, where the first credit tracker is to update the at least one credit counter based on receipt of an in-band interrupt from the first device having the credit information. Other embodiments are described and claimed.

公开(公告)号：US20190033375A1

公开(公告)日：2019-01-31

申请号：US15837462

申请日：2017-12-11

申请人： Intel Corporation

发明人： Enrico D. Carrieri ,  John W. Kitterman ,  Keith A. Jones

IPC分类号： G01R31/3185 ,  G01R31/317

摘要： A Joint Test Access Group (JTAG) device can include a Joint Test Access Group (JTAG) port, transport layer circuitry to provide a communication to and from a debug device, and packet interpreter circuitry communicatively coupled between the JTAG port and the transport layer circuitry, the packet interpreter circuitry to translate data in a packet from the debug device into a sequence of bits to be provided to the JTAG port.

公开(公告)号：US11138083B2

公开(公告)日：2021-10-05

申请号：US16596154

申请日：2019-10-08

申请人： Intel Corporation

发明人： Patrik Eder ,  Rolf H. Kuehnis ,  Enrico D. Carrieri

IPC分类号： G06F11/25 ,  G06F11/267 ,  G01R31/317

摘要： Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.