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    Decoupling Visibility Bins and Render Tile Dimensions for Tiled Rendering
    1.
    发明申请
    Decoupling Visibility Bins and Render Tile Dimensions for Tiled Rendering 有权
    拆分可见性框和渲染瓷砖尺寸进行平铺渲染

    公开(公告)号：US20160171751A1

    公开(公告)日：2016-06-16

    申请号：US14570710

    申请日：2014-12-15

    Applicant: Intel Corporation

    Inventor： Peter L. DOYLE

    IPC: G06T15/40 ,  G06T1/20

    CPC classification number: G06T15/40 ,  G06T1/20 ,  G06T15/005

    Abstract: An apparatus and method are described for decoupling visibility bins and render tile dimensions for tiled rendering. In one embodiment of the invention, a single visibility pass over the scene objects is performed and all the visibility bins are generated in parallel. This allows for high performance when the number of render tiles exceeds the number of visibility bins. The regions upon which visibility testing/recording is done is decoupled from the render tile regions in one embodiment of the invention. This allows a given visibility bin to map to multiple render tiles, thus allowing a fixed number of visibility bins to support any number of render tiles.

    Abstract translation: 描述了一种用于去除可见性容器并为平铺渲染渲染瓷砖尺寸的装置和方法。 在本发明的一个实施例中，执行对场景对象的单个可视性传递，并且并行地生成所有可见性区块。 当渲染图块的数量超过可见性数量的数量时，可以实现高性能。 在本发明的一个实施例中，可见度测试/记录完成的区域与渲染平铺区域分离。 这允许给定的可见性分区映射到多个渲染图块，从而允许固定数量的可见性容器来支持任意数量的渲染图块。

    APPARATUS AND METHOD FOR OPTIMIZED TILE-BASED RENDERING
    3.
    发明申请
    APPARATUS AND METHOD FOR OPTIMIZED TILE-BASED RENDERING 有权

    公开(公告)号：US20210035348A1

    公开(公告)日：2021-02-04

    申请号：US17072253

    申请日：2020-10-16

    Applicant: INTEL CORPORATION

    Inventor： Prasoonkumar SURTI ,  Tomas G. AKENINE-MOLLER ,  David J. COWPERTHWAITE ,  Kun TIAN ,  Peter L. DOYLE ,  Brent E. INSKO ,  Adam T. LAKE

    IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T15/50

    Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

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